FIR Filter Ring Counter Architecture for Lower Power Convolution
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Solution Overview
Problem
Full throughput FIR filters consume a significant amount of power due to power-intensive convolution operations, making it challenging to implement low-power filters with high performance.
Innovation Solution
The FIR filter design incorporates a ring counter with flip-flops in a ring configuration to distribute a single pulse among registers, allowing only one register to process data per clock cycle, and uses multiplexers to change convolution coefficients for each register, reducing power consumption while maintaining high performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all input registers process data simultaneously on each clock cycle, then high throughput is achieved, but power consumption increases significantly
Solution Approach 1:
The patent implements periodic action by using a ring counter to sequentially enable different input registers at different time periods. Instead of all registers operating simultaneously, each register is activated in a cyclic manner, ensuring that only one register processes data at any given clock cycle. This periodic activation maintains full throughput capability while reducing power consumption by keeping other registers in a low-power state.
Solution Approach 2:
The system dynamically switches which input register is active based on the state of the ring counter. The enable signals are dynamically generated to activate only the required register at each clock cycle, allowing the system to adapt its operational state to minimize power consumption while maintaining processing continuity through the sequential activation pattern.
2Productivity
If multiple registers are enabled simultaneously, then parallel processing capability is improved, but clock signal distribution complexity increases
Solution Approach 1:
The ring counter serves as an intermediary device that simplifies clock signal distribution. Instead of directly managing complex clock distribution to multiple registers, the ring counter generates sequential enable signals that act as intermediaries, selectively activating only one register at a time. This intermediary mechanism greatly simplifies the clock distribution network while maintaining the system's parallel processing capability through sequential operation.
3Speed
If convolution operations are performed by all registers, then processing speed is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by sequentially enabling different input registers to perform convolution operations at different time periods. Each register performs its convolution operation when enabled by the ring counter, ensuring continuous processing across all registers over time while only one register consumes significant power at any instant. This maintains overall processing speed while dramatically reducing instantaneous and average power consumption.
Solution Approach 2:
The system effectively discards the active state of all registers except one at any given time, with the understanding that other registers will recover and become active in subsequent clock cycles. This cyclic discarding and recovering of register states allows the system to maintain processing throughput while minimizing power consumption by ensuring only necessary circuitry is active at any moment.
Data Source
AI summary
A finite impulse response (FIR) filter includes a plurality of registers. The data input terminal of each register is directly coupled to the input of the FIR filter. A new data value is passed to each register on each clock cycle of a filter clock signal. Only one of the registers processes the data value on each clock cycle. A ring counter is coupled to the registers and determines which register processes the data value on each dock cycle.