FIR Filter Architecture Using Running Sums Instead of Multipliers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Finite Impulse Response (FIR) filters require significant computational resources and are costly due to the need for multiple multiplications, which is a limitation in digital signal processing, especially in applications like ultrasound systems where cost and resource conservation are crucial.
Innovation Solution
Implementing FIR filters as a sum of individual component running-sum filters, where the desired impulse response is decomposed into rectangular components, allowing for the use of subtraction and addition operations instead of multiplications, and enabling the implementation of arbitrary impulse response shapes and lengths using minimal hardware resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional FIR filter implementation using multipliers is used, then filter accuracy and frequency response characteristics are improved, but chip cost and manufacturing cost increase significantly
Solution Approach 1:
The patent replaces expensive multiplier circuits with inexpensive adder circuits. Adders are fundamentally cheaper to implement in hardware than multipliers, requiring fewer logic gates and less chip area. The invention uses a series of adders arranged in a specific configuration to achieve multiplication-like functionality through repeated addition, thereby dramatically reducing chip cost and manufacturing cost while maintaining filter accuracy.
Solution Approach 2:
The patent substitutes the mechanical/multiplicative operation with an additive operation. Instead of using multiplier circuits that perform direct multiplication, the invention uses adder circuits that perform repeated addition to achieve the same filtering effect. This substitution of the fundamental arithmetic operation reduces hardware complexity and cost.
2Measurement precision
If the number of filter coefficients (taps) is increased to improve frequency response, then filter performance is improved, but computational complexity and number of multiplications increase
Solution Approach 1:
The patent segments the filter implementation into multiple stages of adders working in parallel or sequence. Instead of using a single complex multiplier for each coefficient, the invention breaks down the multiplication operation into multiple simpler addition operations distributed across different stages. This segmentation reduces the computational complexity at each stage while maintaining the overall filtering performance.
Solution Approach 2:
The patent merges multiple addition operations into a unified adder network structure. By combining the partial sums from different coefficient multiplications into a single accumulation path using adders, the invention reduces the total number of computational elements needed. The merging of computational paths allows the system to handle more filter coefficients without proportionally increasing complexity.
3Measurement precision
If multiplier circuits are used to achieve desired filter response, then filter quality is improved, but chip area and IC resources are consumed
Solution Approach 1:
The patent replaces area-intensive multiplier circuits with compact adder circuits. Adders occupy significantly less chip area than multipliers because they require fewer logic gates and can be implemented more efficiently in standard cell libraries. The invention achieves the necessary computational functionality using this area-efficient adder-based approach, thereby reducing overall chip area consumption.
Solution Approach 2:
The patent changes the fundamental arithmetic parameter from multiplication to addition. By altering the mathematical operation from multiply-accumulate to add-accumulate, the invention fundamentally changes the hardware parameter requirements. Adders have smaller area footprints and lower power consumption compared to multipliers, thus achieving the same filter quality with reduced chip area.
4Device complexity
If symmetric properties of filter coefficients are exploited to reduce multipliers, then number of multipliers is reduced by factor of 2, but reduction is insufficient for many applications
Solution Approach 1:
The patent applies a universal adder-based substitution that works for all filter types regardless of coefficient symmetry. Unlike symmetry-exploitation methods that require specific filter designs, the adder-based approach can implement any FIR filter configuration without modification. This provides full adaptability and versatility across different applications while achieving greater reduction in computational elements than symmetry-based methods alone.
Data Source
AI summary
A finite impulse response filter is implemented as a sum of individual component, running-sum filters. The sum of all of the component filters required for a desired filter response is calculated in an accumulator and only the component filters' update terms, which are the difference between a new and an old discarded sample, is calculated for each component filter. A desired impulse response is decomposed into a sum of rectangular impulse responses of equal height, each of which implemented as a running sum requiring a subtraction and an addition. Using circuits running at a multiple of the sampling clock, multiple running sums may be implemented on the same hardware. A whole filter of arbitrary impulse response shapes and lengths may be implemented using memory and two arithmetic units. Two or more such filters may be cascaded to obtain a better approximation of the desired frequency characteristic. The invention saves significant chip resources and manufacturing costs.