Multi-Stage FIR Interpolation Without Dual-Port FIFO Memory
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Solution Overview
Problem
High-order digital filters, particularly interpolation filters, require significant computational resources and chip area due to the need for dual-port FIFO memory to manage cascaded sub-filters operating at different repetition rates, leading to increased cost and power consumption, especially in portable systems.
Innovation Solution
Configuring interpolation filters as a cascade arrangement of simpler sub-filters operating in reverse order, with added delays to ensure computational independence, eliminating the need for dual-port FIFO memory by using prior filtering results and increased memory for correct sequencing of output signal samples.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-order FIR filters are implemented with many taps to achieve high filtering performance, then filtering performance is improved, but chip area and computational complexity increase significantly
Solution Approach 1:
The high-order FIR filter is divided into multiple cascaded stages, each containing several taps. The filter coefficients are segmented and distributed across these stages, allowing the filter to achieve high-order performance while reducing the area requirement compared to a single-stage implementation. Each stage processes a portion of the computation at a reduced repetition rate.
Solution Approach 2:
The patent implements dynamic operation where different stages operate at different repetition rates. The first stage operates at a lower repetition rate than subsequent stages, allowing computational work to be distributed over time. This dynamic approach reduces the peak computational demand and allows for smaller, more area-efficient hardware implementation while maintaining the required filtering performance.
2Measurement precision
If high-order FIR filters are implemented with many taps to achieve high filtering performance, then filtering performance is improved, but power consumption increases
Solution Approach 1:
By segmenting the filter into cascaded stages with distributed taps, the computational load is spread across multiple smaller units rather than one large unit. This segmentation allows for more efficient power utilization as each stage can be optimized independently and operates at appropriate repetition rates.
Solution Approach 2:
The dynamic operation where stages run at different repetition rates allows the system to consume power more efficiently. Earlier stages that require less computation run at lower rates, while later stages that require more computation run at higher rates. This dynamic scheduling optimizes the balance between computational throughput and power consumption.
3Productivity
If cascaded sub-filters operate at different repetition rates to reduce computational load, then productivity is improved, but device complexity increases due to dual-port FIFO memory requirements
Solution Approach 1:
The patent merges the memory structures by having multiple stages share common delay elements and memory resources. Instead of each stage having separate FIFO memory, the stages share the delay line memory, which is accessed at different times. This merging eliminates the need for dual-port FIFO memory while still allowing different stages to operate at different repetition rates.
Solution Approach 2:
The delay elements and memory structures serve multiple functions: they provide buffering between stages operating at different rates, store filter coefficients, and implement the delay required for FIR filtering. This multi-functionality reduces the overall complexity by eliminating dedicated dual-port FIFO memory structures.
4Productivity
If cascaded sub-filters operate at different repetition rates to reduce computational load, then productivity is improved, but manufacturing cost increases
Solution Approach 1:
By merging memory resources and eliminating dual-port FIFO structures, the patent reduces the manufacturing complexity and associated costs. The shared delay line implementation requires fewer memory resources and simpler control logic, leading to lower manufacturing costs while maintaining the productivity benefits of different repetition rates.
Data Source
AI summary
An interpolation filter without a FIFO memory is configured as a cascade arrangement of simpler interpolation sub-filters that are operated in reverse order. The interpolation sub-filter that produces the highest sampling frequency is operated first, followed by interpolation sub-filters that operate at successively lower sampling frequencies. Computational independence of the cascaded sub-filters is guaranteed by adding delays to sampled and filtered signals. Delays are implemented by operating each of the cascaded sub-filters using prior filtering results that are computed during a previous sampling interval. A small increment to random-access memory is required for storing the successively delayed signals. The digital signal processor performing the filtering process is stalled for one clock cycle at the time a filtered signal sample is outputted so that the outputted signal sample can be produced without a timing conflict.