FIR-Based PAM Signal Generator for Fast Emphasis Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing signal generators face challenges in flexibly increasing the number of taps while achieving high-speed emphasis switching, due to fixed IC design and hardware switches, which limits adaptability to changing standards and increases mounting area.
Innovation Solution
A signal generator with an emphasis addition circuit featuring multiple FIR filter units configured on a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC), allowing for flexible tap value setting and high-speed emphasis switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of taps is increased to improve emphasis switching capability, then the adaptability to changing standards is improved, but the mounting area increases and flexibility is reduced due to fixed IC design
Solution Approach 1:
The patent implements dynamic reconfigurability by using an FPGA-based emphasis addition circuit that can change its tap configuration in real-time based on switching requests from the DUT. The system transitions from a static IC design to a dynamic reconfigurable architecture, allowing the number of taps to be adjusted without physical hardware changes, thereby improving adaptability while maintaining compact mounting area.
Solution Approach 2:
The system changes the operational parameters of the emphasis addition circuit by allowing dynamic modification of tap values and filter coefficients through software control. This parameter-based reconfiguration enables the same hardware to adapt to different standards and requirements without physical modification, resolving the contradiction between adaptability and mounting area.
2Speed
If hardware switches are introduced for emphasis switching, then the switching speed is improved, but the mounting area increases and multiple taps become difficult to realize
Solution Approach 1:
The patent replaces mechanical hardware switches with a software-controlled reconfiguration mechanism implemented in FPGA logic. This substitution eliminates the need for physical switching components while maintaining high-speed switching capability through digital logic reconfiguration, thereby reducing mounting area while preserving switching speed performance.
Solution Approach 2:
The system achieves high-speed emphasis switching through dynamic reconfiguration of the FPGA logic structure rather than using static hardware switches. The reconfigurable architecture allows rapid switching by changing the active filter taps through control signals, eliminating the need for physical switch components and their associated mounting area.
3Adaptability or versatility
If the number of taps is increased to improve emphasis switching capability, then the emphasis switching flexibility is improved, but the hardware complexity increases making it difficult to realize multiple taps
Solution Approach 1:
The patent implements a universal emphasis addition circuit on FPGA that can perform multiple functions by reconfiguring the same hardware resources. The single reconfigurable circuit can realize different numbers of taps and different filter configurations, eliminating the need for separate hardware for each tap configuration and thereby reducing overall hardware complexity while improving flexibility.
Solution Approach 2:
The system achieves multiple tap configurations by changing the operational parameters of the FIR filter through software control rather than increasing hardware complexity. The same hardware structure can be reconfigured to support different numbers of taps by modifying the filter coefficients and tap enable signals, thereby实现ing flexibility without proportional increase in hardware complexity.
Data Source
AI summary
There are provided a signal generator capable of flexibly increasing the number of taps while realizing high-speed emphasis switching and an emphasis switching method using the signal generator. A signal generator includes: an emphasis addition circuit including at least one finite impulse response (FIR) filter unit that generates an emphasis waveform pattern by adding an emphasis to a pattern of a pulse amplitude modulation (PAM) signal including multi-values which are two or more values; and a tap value setting unit that switches M tap values C(0), C(−1), . . . , and C(1−M) and sets the M tap values C(0), C(−1), . . . , and C(1−M) to each FIR filter unit according to an emphasis switching request from a DUT 100. The FIR filter unit is configured on an FPGA or an ASIC.


