FIR-Based Data Phase Tracking for Clock Synchronization
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Solution Overview
Problem
Conventional communication devices require complex configurations and additional costly external circuits like analog VCOs, filters, and D/A converters for clock synchronization, which complicates the design and increases noise characteristics.
Innovation Solution
A data phase tracking device using an FIR filter to convolute sampled data with adjustable tap coefficients, detecting phase differences, and adjusting these coefficients to synchronize the sampling timing with the signal waveform, eliminating the need for external analog circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock synchronization using PLL and analog VCO is used, then clock synchronization is achieved, but device complexity increases and noise characteristics worsen
Solution Approach 1:
The patent replaces the mechanical/analog PLL system with a digital signal processing approach using an FIR filter. The tap coefficients of the FIR filter are adjusted to achieve phase tracking, substituting the need for analog VCO, filters, and D/A converters with purely digital operations. This substitution eliminates external analog circuits while maintaining clock synchronization functionality.
Solution Approach 2:
The patent creates a digital model of the clock signal through the FIR filter output, which copies the essential timing characteristics of the original reception signal clock. By adjusting tap coefficients, this digital copy tracks the phase of the original clock without requiring physical analog synchronization components.
2Reliability
If analog VCO and external analog circuits are used for clock synchronization, then phase locking is achieved, but manufacturing cost increases
Solution Approach 1:
The patent substitutes expensive analog components (VCO, external filters, D/A converters) with digital signal processing operations. The FIR filter with adjustable tap coefficients performs phase tracking entirely in the digital domain, eliminating the need for costly analog hardware while maintaining phase locking capability.
Solution Approach 2:
The patent uses computationally inexpensive digital operations (FIR filtering with tap coefficient adjustment) to replace expensive analog components. The digital processing approach consumes minimal resources and can be implemented efficiently in software or simple hardware, making the system much more cost-effective than analog alternatives.
3Reliability
If analog VCO is used for clock generation, then clock signal is produced, but noise characteristics deteriorate
Solution Approach 1:
The patent replaces the noisy analog VCO with a digital signal processing approach. The FIR filter operates on sampled data in the digital domain, completely avoiding the thermal noise and phase noise inherent in analog oscillators. This substitution eliminates the primary noise source while maintaining clock signal generation functionality.
Solution Approach 2:
The patent generates a clean digital copy of the clock signal through the FIR filter output, which derives timing information from the received signal itself rather than using a separate noisy oscillator. This copied timing signal inherits the signal's inherent coherence without adding analog noise.
Data Source
AI summary
An FIR filter convolutes sampled data obtained by sampling a reception signal with tap coefficients. A phase difference detector detects a phase difference between a synchronization timing of a signal waveform estimated from an output signal of the FIR filter and a sampling timing of the output signal. A tap coefficient adjuster adjusts the tap coefficients so as to reduce the phase difference detected by the phase difference detector and causes the sampling timing of the output signal of the FIR filter to track the synchronization timing.