Firmware Program Flow Monitoring Using CRC Code Sequence Checks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Automotive radar systems require stringent execution of program instructions to ensure safety, but existing methods struggle to consistently maintain the intended sequence due to hardware errors or interference, and designing processors to higher safety standards is costly and complex.
Innovation Solution
Implementing a Program Flow Monitoring (PFM) unit that generates an error-checking value using cyclic redundancy check (CRC) based on code values, which compares the executed sequence to an expected return value, allowing for timely detection and correction of deviations from the intended sequence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processors are designed to higher safety standards (ISO 26262), then reliability of instruction execution sequence is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The system separates the safety monitoring function from the main processor by introducing an independent PFM unit. This segmentation allows the processor to focus on executing instructions while the PFM unit independently verifies the execution sequence, thus improving reliability without significantly increasing processor complexity.
Solution Approach 2:
The PFM unit acts as an intermediary between the processor and the safety verification process. It receives code values from the processor, generates error-checking values independently, and compares them against expected return values, thereby mediating the safety verification without requiring the processor itself to be redesigned to higher standards.
2Reliability
If processors are designed to higher safety standards (ISO 26262), then reliability of instruction execution sequence is improved, but manufacturing cost increases
Solution Approach 1:
By segmenting the safety monitoring function into a separate PFM unit, the main processor can be manufactured to lower standards (ISO 16949), reducing manufacturing costs. The PFM unit, which can be implemented as a simpler hardware component or even software module, handles the safety verification independently.
Solution Approach 2:
The PFM unit can be implemented using less expensive components compared to redesigning the entire processor to higher safety standards. The error-checking mechanism uses straightforward CRC calculations and comparisons, which can be implemented with minimal hardware resources or even in software, providing cost-effective safety verification.
3Reliability
If safety monitoring units are employed to perform tests, then safety is improved, but device complexity increases
Solution Approach 1:
The PFM unit is designed to be versatile and can monitor any sequence of code values executed by the processor, regardless of the specific application or instruction set. This universal approach allows a single PFM unit to provide safety monitoring across different functions and modules, reducing overall system complexity compared to having dedicated safety monitoring for each function.
Solution Approach 2:
The PFM unit performs self-verification by independently generating error-checking values from the code values it receives and comparing them against pre-stored expected return values. This self-service mechanism eliminates the need for external safety verification systems or manual testing, simplifying the overall system architecture while maintaining safety monitoring capabilities.
Data Source
AI summary
The present disclosure relates to a safety system having a memory unit configured to store a series of executable instructions. In some embodiments, the executable instructions are grouped into code parts, and each code part is assigned a predefined code value. A processor is configured to execute the series of executable instructions, and to output the predefined code values respectively as the code parts are executed. A program flow monitoring (PFM) unit is configured to respectively receive the predefined code values from the processor, such that the PFM unit generates an error-checking value from the predefined code values. A verification unit is configured to compare the error-checking value to an expected return value to determine whether the series of executable instructions executed properly.