Hardware Monitors Verify Firmware Binary Images
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Solution Overview
Problem
Existing methods are inefficient in detecting illegal firmware instructions in firmware binary images, as they rely on reverse engineering, which is tedious and unreliable, making it difficult to identify and correct errors or bugs before loading the firmware into electronic devices.
Innovation Solution
The implementation of hardware monitors that use monitor and detection logic to detect when the firmware execution starts and stops, and assertion evaluation logic to determine if an illegal firmware instruction has been decoded, in conjunction with formal verification tools to exhaustively verify the absence of illegal instructions in the firmware binary image.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reverse engineering methods are used to detect illegal firmware instructions, then detection capability is provided, but the process is tedious and unreliable with low efficiency
Solution Approach 1:
The patent replaces manual reverse engineering processes with automated hardware monitoring and formal verification systems. Hardware monitors automatically track firmware execution states, and formal verification tools mathematically prove the absence of illegal instructions, eliminating the tedious and error-prone manual analysis while significantly improving both reliability and efficiency
Solution Approach 2:
The patent introduces hardware monitors as intermediary components that sit between the firmware execution and the verification process. These monitors capture execution states and provide structured data to formal verification tools, serving as a bridge that transforms unstructured firmware behavior into verifiable information, thereby improving detection reliability without manual intervention
2Reliability
If simulation-based methods are used to detect firmware errors, then some bugs can be identified, but illegal instructions are difficult to detect and verification is incomplete
Solution Approach 1:
The patent performs preliminary actions by setting up hardware monitors before firmware execution begins. These monitors are pre-configured to track specific execution states and illegal instruction patterns, enabling comprehensive detection from the start of execution rather than requiring complex post-execution analysis or multiple simulation scenarios
Solution Approach 2:
The patent replaces complex simulation-based verification with hardware-based monitoring and formal mathematical verification. This substitution provides complete and rigorous verification of firmware correctness without the limitations of simulation, achieving detection completeness while managing complexity through automated tools
3Productivity
If formal verification with hardware monitors is used, then verification efficiency and completeness are improved, but hardware design complexity increases
Solution Approach 1:
The patent segments the verification system into distinct modular components: hardware monitors for execution state tracking, assertion evaluation logic for property verification, and formal verification tools for mathematical proof. This segmentation allows each component to be independently designed, tested, and optimized, improving overall verification efficiency while managing hardware complexity through modularity
Solution Approach 2:
The hardware monitors are designed with multi-functionality, serving both as execution state trackers and as sources of verification data for multiple assertion checks. This universal design reduces the need for separate dedicated components for each verification function, improving efficiency while minimizing the increase in hardware complexity
Data Source
AI summary
Described herein are hardware monitors arranged to detect illegal firmware instructions in a firmware binary image using a hardware design and one or more formal assertions. The hardware monitors include monitor and detection logic configured to detect when an instantiation of the hardware design has started and/or stopped execution of the firmware and to detect when the instantiation of the hardware design has decoded an illegal firmware instruction. The hardware monitors also include assertion evaluation logic configured to determine whether the firmware binary image comprises an illegal firmware instruction by evaluating one or more assertions that assert that if a stop of firmware execution has been detected, that a decode of an illegal firmware instruction has (or has not) been detected. The hardware monitor may be used by a formal verification tool to exhaustively verify that the firmware boot image does not comprise an illegal firmware instruction, or during simulation to detect illegal firmware instructions in a firmware boot image.