Dynamic Firmware Image Sequencing via Hardware Register

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Solution Overview

Problem

The development and testing of firmware for devices like smartphones and automobiles are time-consuming and costly, especially when updating firmware stored in read-only memory, as it often requires re-testing all functionality, which can be inefficient and expensive.

Innovation Solution

A system with multiple firmware images, each with a distinct entry point, utilizing a hardware register and an external controller to manage transitions between these images, allowing the processor to fetch instructions from different firmware images without power cycling, thereby preserving prior investments in development and testing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If firmware is stored in read-only memory (ROM) and updated by physically replacing the ROM, then firmware reliability is improved, but test time and expense increase significantly

Engineering Contradiction:

Improvefirmware reliabilityVSAvoidtest time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The firmware is divided into multiple separate images, each stored in its own designated memory region. This segmentation allows individual firmware images to be tested and validated independently before being loaded into the processor, reducing the need for comprehensive re-testing when updates are deployed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Firmware images are pre-tested and validated in isolation before being loaded into the processor. The external controller loads complete, pre-validated firmware images into memory, ensuring that each image is ready for execution without requiring extensive post-loading testing, thus reducing test time while maintaining reliability.

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If new features are added to firmware via new source code, then functionality is improved, but test time and expense increase due to need for full re-testing

Engineering Contradiction:

Improvefirmware functionalityVSAvoidtest time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system changes the parameter of firmware delivery from monolithic updates to modular image sequences. By controlling the execution sequence of firmware images through the external controller and hardware register mechanism, the system can deploy new features in isolated images that have been pre-tested, avoiding the need to re-test entire firmware suites.

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If multiple firmware images are stored in memory with distinct entry points, then firmware adaptability is improved, but device complexity increases

Engineering Contradiction:

Improvefirmware adaptabilityVSAvoidsystem complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

An external controller acts as an intermediary between the processor and the memory containing multiple firmware images. This external controller manages the complexity of sequencing and loading firmware images by handling all interactions with the hardware register and memory, keeping the processor itself simple while enabling sophisticated firmware management capabilities.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The hardware register automatically retains the firmware image entry point information between processor resets without requiring complex control logic. The external controller simply writes the entry point to the hardware register, and the system self-manages the sequencing through the reset mechanism, reducing the need for complex firmware image management software.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS12169720B2System with dynamically selectable firmware image sequencing for production test, debug, prototyping

Publication Date: 2024.12.17 CIRRUS LOGIC INC

AI summary

A system has a memory programmed with multiple firmware images each having an associated distinct entry point, a processor, a writable hardware register, and a controller external to the processor that, prior to each reset of a sequence of resets of the processor, reads the entry point of a firmware image from the hardware register and causes the processor to begin fetching instructions at the entry point read from the hardware register. The firmware images include boot, mission mode, and at least one other firmware image. The memory may be writeable with a modifiable version of a post-production mission mode, debug, prototype, or patched ROM firmware image. A second controller writes a second entry point to the hardware register prior to an initial reset such that the external controller reads the second entry point and causes fetching instructions at the second entry point rather than the initial entry point.