Firmware Mark Table for Multi-Region Memory Error Correction

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Solution Overview

Problem

Current computer memory error correction systems are limited in their ability to efficiently detect and correct errors across multiple regions of memory, often relying on hardware mark tables that can only store single error indications and are unable to handle broader error sets, leading to reduced memory reliability and predictability.

Innovation Solution

The proposed method involves a firmware mark table that stores region sizes, match addresses, and mark locations, allowing for error correction by generating masks based on region sizes to determine if a read address falls within a specified memory region, enabling efficient error detection and correction across multiple error types within computer memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If hardware mark tables are used for error correction, then error detection capability is provided, but the system can only store single error indications and cannot handle broader error sets

Engineering Contradiction:
Improveerror handling capabilityVSAvoidmemory reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the error correction functionality by dividing the mark table into multiple entries, where each entry can store error information for a specific memory region. This segmentation allows the system to handle multiple error indications simultaneously, with each entry containing a region size field, match address field, and mark location field specific to its region, thereby increasing adaptability without compromising reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent adds a regional dimension to error correction by introducing region size and match address fields alongside the traditional mark location. This dimensional expansion transforms the mark table from a simple error indicator into a region-aware error management structure, enabling the system to handle broader error sets across different memory regions while maintaining correction reliability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If firmware mark tables with region sizes and match addresses are implemented, then error detection across multiple regions is enabled, but device complexity increases

Engineering Contradiction:
Improvemulti-region error detectionVSAvoidmark table structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates a universal mark table entry structure that can handle multiple error types and regions through standardized fields (region size, match address, mark location). This universal structure allows the same mark table mechanism to serve multiple regions and error conditions, enabling multi-region error detection while avoiding the need for separate complex structures for each region, thus managing device complexity effectively

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Measurement precision

If mask generation based on region size is performed for each mark table entry, then precise error location determination is achieved, but processing time increases

Engineering Contradiction:
Improveerror location precisionVSAvoiderror correction time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by pre-organizing error information into structured mark table entries with predefined region sizes and match addresses during memory initialization or error detection phases. This preliminary structuring allows subsequent error location determinations to proceed efficiently through direct comparison operations rather than complex calculations, achieving precise error location while minimizing processing time during actual read operations

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10971246B2Performing error correction in computer memory
Publication Date: 2021.04.06 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10971246B2 patent drawing
  • US10971246B2 patent drawing
  • US10971246B2 patent drawing

AI summary

Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.