Trusted Firmware Resilience Engine for Secure Chip Isolation
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Solution Overview
Problem
Existing cyber resilience solutions for cyber-physical systems are costly and do not provide comprehensive protection against sophisticated attacks, especially in resource-constrained devices, necessitating the need for innovative approaches that leverage existing processor capabilities to enhance security and resilience.
Innovation Solution
A semiconductor chip with a firmware that implements a resilience engine within a trusted execution environment, utilizing existing processor features like privilege levels and memory protection mechanisms to provide secure isolation and periodic integrity checks, enabling robust verification and recovery mechanisms without additional hardware components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware-based security measures (dedicated security chips or modules) are implemented, then system security and resilience are improved, but device complexity and cost increase
Solution Approach 1:
The patent merges the security resilience engine with the existing processor by utilizing the processor's built-in trusted execution environment (TEE). Instead of adding a separate security chip or module, the resilience engine is integrated into the processor's secure world, combining security functions with the existing processing architecture. This eliminates the need for additional hardware components while maintaining security effectiveness.
Solution Approach 2:
The patent makes the existing processor serve multiple functions by enabling it to execute both secure resilience engine code and regular application code through the TEE mechanism. The processor's secure world is used universally to provide both security isolation and the resilience engine functionality, eliminating the need for dedicated security hardware and reducing overall device complexity.
2Reliability
If dedicated security hardware is added to provide comprehensive protection, then protection coverage is improved, but cost increases
Solution Approach 1:
The patent enables the processor to provide its own security services through the trusted execution environment. The processor's secure world automatically provides isolation, authentication, and integrity verification capabilities without requiring external security hardware. This self-service approach eliminates the need for additional security components and reduces manufacturing costs while maintaining comprehensive protection coverage.
3Reliability
If additional hardware components are added for resilience engine functionality, then security functionality is improved, but ease of updates and maintenance worsens
Solution Approach 1:
The patent replaces the mechanical/hardware-based security system with a software-based resilience engine that runs within the processor's TEE. Instead of using fixed hardware security modules that require physical access for updates, the resilience engine is implemented as software that can be remotely updated and maintained through standard firmware update mechanisms, significantly improving ease of updates and maintenance.
Data Source
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AI summary
The Semiconductor chip comprises at least a processor (MCUO, RISC) and a trusted execution environment (SW; SHP, IHP, STP, ITP) and a firmware configured to run on the semiconductor chip and the firmware is configured to run a resilience engine (RE) that is realized within the trusted execution environment (SW; SHP, IHP, STP, ITP).