Firmware Verification Circuit for TOC-TOU Image Integrity
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Solution Overview
Problem
The existing platform firmware resiliency (PFR) mechanism fails to prevent side channel attacks and is inefficient due to time-consuming integrity verification of static executable images, which are verified only once at power-on, leaving the system vulnerable to tampering and performance degradation with increasing firmware elements.
Innovation Solution
A dual verification mechanism that verifies executable images at time of check (TOC) and time of use (TOU) using a hash tree and encryption, ensuring integrity and security by stopping execution if tampering is detected, and optimizing verification time through selective hash calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PFR mechanism verifies all executable images from static memories at T-1 phase before host reset, then integrity verification is performed, but the verification process costs a lot of time and increases T-1 phase duration
Solution Approach 1:
The verification process is segmented into two distinct phases: T-1 phase verification of root hash values for all executable images, and T-0 phase verification of specific code blocks during host reset. This segmentation allows the system to verify critical integrity information (root hash) quickly at T-1 phase without verifying entire images, while detailed verification occurs at T-0 phase when images are actually loaded, thus reducing T-1 phase verification time while maintaining reliability.
Solution Approach 2:
The system performs preliminary verification of root hash values at T-1 phase before host reset is released. This preliminary action establishes a baseline integrity check that is computationally efficient, allowing the system to quickly identify obviously compromised images without performing full verification, thereby reducing the time cost of the T-1 phase while ensuring that only images with valid root hashes proceed to execution.
2Loss of time
If the PFR architecture verifies static images only once at TOC (T-1 phase), then verification is completed quickly, but the system cannot handle side channel attacks that modify static memory after verification
Solution Approach 1:
The verification action continues from T-1 phase through T-0 phase and extends into T phase during host reset. The system continuously verifies integrity by checking root hash values at T-1 phase, then verifying specific code blocks at T-0 phase when images are loaded into dynamic memory, and maintaining verification during execution at T phase. This continuous verification ensures that any modifications to static memory after initial verification are detected, providing ongoing security against side channel attacks while managing verification time efficiently.
Solution Approach 2:
The system implements feedback mechanisms where verification results from T-1 phase (root hash validation) inform the T-0 phase verification process, and verification results during T phase feed back into system security decisions. If verification fails at any stage, the system can trigger corrective actions such as halting execution or initiating recovery procedures. This feedback loop ensures that security verification is not a one-time event but an ongoing process that adapts to detected threats, maintaining both security and efficiency.
3Adaptability or versatility
If the number of firmware elements increases, then system functionality is enhanced, but the time spent in T-1 phase verification increases proportionally
Solution Approach 1:
The system extracts and separates the verification of root hash values from the verification of entire executable images. By taking out only the critical root hash information for verification at T-1 phase and deferring detailed image verification to T-0 phase when images are actually loaded and executed, the system can support an increasing number of firmware elements without proportionally increasing T-1 phase verification time. This extraction approach focuses verification effort on the most critical integrity checks while reducing overall verification overhead.
Data Source
AI summary
A data security verification method and an electronic apparatus are provided. In the data security verification method, when the electronic apparatus is powered on, a verification circuit verifies integrity of an executable image in a storage device. If verification fails, the verification circuit stops a host processor from executing the executable image. If the verification is successful, the verification circuit releases a host reset, and a processor reads and executes the executable image. When the processor reads the executable image, the verification circuit re-verifies the executable image, and the processor executes the executable image according to a verification result.