First-Metal Local Interconnect Layout for Lower Standard Cell Height
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor technologies face challenges in reducing the height of standard cells while maintaining effective local interconnects, often requiring additional photolithography masks that increase process risk and fabrication costs, especially when using extreme ultraviolet photolithography.
Innovation Solution
A method is introduced to form metal lines in the first metal layer over front-end-of-line structures, where the second metal line acts as both a metal line and a local interconnect by extending perpendicular to connect the gate and source/drain contact vias, eliminating the need for additional photolithography masks below the first metal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional photolithography masks are used to form local interconnect below the first metal layer, then local interconnect can be formed, but process risk and fabrication cost increase
Solution Approach 1:
The patent merges the local interconnect formation with the first metal layer by forming the local interconnect and the first metal layer simultaneously in the same metal layer, eliminating the need for separate photolithography masks and processes below the first metal layer
Solution Approach 2:
The first metal layer serves dual functions: it provides both the local interconnect (for connecting gates and sources/drains) and the metal interconnect lines, allowing one layer to perform multiple functions that traditionally required separate structures
2Length of stationary object
If the number of metal lines is reduced to lower cell height, then cell height decreases, but forming local interconnect becomes more difficult
Solution Approach 1:
The first metal layer is designed to serve multiple purposes: it creates local interconnects for device connections and simultaneously provides metal interconnect lines for signal routing, eliminating the need for additional metal layers or complex configurations to achieve low cell height
3Reliability
If additional photolithography processes are performed, then local interconnect can be formed below first metal layer, but manufacturing efficiency decreases and costs increase
Solution Approach 1:
The patent combines the local interconnect formation process with the first metal layer deposition process, performing both functions in a single photolithography and metal deposition sequence, thereby eliminating additional manufacturing steps and improving productivity
Data Source
AI summary
Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a first metal line extending along a first direction, a second metal line lengthwise aligned with and spaced apart from the first metal line, and a third metal line extending along the first direction. The third metal line includes a branch extending along a second direction perpendicular to the first direction and the branch partially extends between the first metal line and the second metal line.