Fishbone FET Channel Structure for Drive Current and Heat Dissipation
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Solution Overview
Problem
Current field effect transistors (FETs), such as FinFETs and nanosheet FETs, face challenges in scaling and achieving balanced drive current due to high aspect ratios and surface orientations, leading to difficulties in lithography and electrostatic control, which affects their performance and reliability.
Innovation Solution
A semiconductor device with a channel structure combining FinFET and nanosheet FET features, forming a fishbone structure with a first fin extending in one direction and second fins protruding from it, enhancing effective channel width and heat dissipation, and using a superlattice epitaxy structure with selective etching to fabricate the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If FinFET structure is used to increase effective channel width, then drive current is improved, but aspect ratio becomes high leading to lithography difficulties
Solution Approach 1:
The channel is divided into multiple fins extending in the first direction, with additional fins protruding in the second direction. This segmentation allows the channel width to be increased through multiple discrete fin structures rather than a single high aspect ratio fin, making the structure more amenable to lithography processes.
Solution Approach 2:
The channel structure transitions from a single-direction fin extension to a two-dimensional fin array with fins extending in the first direction and additional fins protruding in the second direction. This dimensional expansion increases effective channel width without requiring excessive height, thereby reducing the aspect ratio while maintaining or improving drive current.
2Reliability
If nanosheet FET structure is used to improve electrostatic control, then device reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The gate structure provides electrostatic control over the channel region similar to nanosheet FETs, while the fabrication process uses planar-like epitaxial growth and etching steps that are more compatible with existing manufacturing infrastructure. The multi-fin structure allows the same gate to control multiple channel paths, achieving enhanced electrostatic control without proportionally increasing fabrication complexity.
3Power
If channel width is increased to improve drive current, then power delivery is improved, but heat dissipation becomes more difficult
Solution Approach 1:
The channel is segmented into multiple fins separated by spacing, with gaps between adjacent fins. This segmentation allows heat generated in each fin to dissipate independently through the spacing regions, preventing heat accumulation that would occur in a solid wide channel, while still maintaining high effective channel width for improved drive current.
Solution Approach 2:
The fin array structure creates a porous-like configuration with spacing between fins, allowing heat to escape through the voids and improving thermal management. The spacing acts as thermal pathways, enabling heat dissipation from the channel region without requiring the channel to be a solid continuous structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The combined Fin+NS FET structure increases effective channel width, balances drive current between NMOS and PMOS devices, and improves heat dissipation, addressing scaling challenges and reliability issues in FETs.
Implementation Method 1
growing a superlattice epitaxy structure, the superlattice epitaxy structure including more than one first epitaxy layers and at least one second epitaxy layer grown alternatingly one over another
Implementation Method 2
etching the more than one first epitaxy layers from the superlattice epitaxy structure
Data Source
AI summary
According to one or more embodiments of the present disclosure, a semiconductor device is described. The semiconductor device may include a substrate, a channel portion on the substrate between a source region and a drain region, and a gate on the channel. The channel portion may include a first portion extending in a first direction and at least one second portion protruding from the first portion in a second direction crossing the first portion.