Fishbone Nanosheet Gate Layout for Tighter Semiconductor Scaling
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Solution Overview
Problem
Nanosheet devices face challenges in aggressive scaling down due to larger minimum channel dimensions compared to FinFET devices, leading to manufacturing complexities and constraints in lithography processes, particularly in separating adjacent gates and epitaxial source/drain structures.
Innovation Solution
A nanosheet device with a fish bone structure is introduced, utilizing a dummy spacer between adjacent semiconductor layer stacks to reduce device size and mitigate overlay shifting issues during fabrication, by separating same-type metal gates and epitaxial source/drain features, thereby reducing the distance between stacks and enhancing manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nanosheet devices are used to achieve better gate control performance, then device performance is improved, but the minimum channel dimension becomes much larger than FinFET devices
Solution Approach 1:
The patent divides the channel into multiple discrete nanosheet segments stacked vertically, allowing the gate to control each segment independently while maintaining a compact lateral footprint. This segmentation enables better gate control performance without requiring larger minimum channel dimensions, as the vertical stacking achieves the needed control in a three-dimensional configuration rather than expanding the lateral channel size.
Solution Approach 2:
The patent transitions from two-dimensional planar channel structures to three-dimensional vertically-stacked nanosheet structures. By stacking multiple nanosheets in the vertical dimension, the device achieves enhanced gate control through increased gate-channel interface area while maintaining a small lateral footprint, thus improving gate control performance without increasing the minimum channel dimension.
2Length of moving object
If aggressive scaling down is implemented to reduce device size, then device dimensions are reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the device into modular components (nanosheet stacks, gates, source/drain regions) that can be formed using standardized fabrication processes. This modular segmentation allows aggressive scaling by repeating the same basic unit multiple times in vertical stacking, thereby reducing overall device dimensions while avoiding the need to develop entirely new manufacturing processes for each scaled-down feature.
Solution Approach 2:
The patent implements nested structures where multiple nanosheets are stacked within a compact vertical space, with gates wrapping around or positioned adjacent to each nanosheet. This nesting approach enables aggressive scaling by fitting multiple functional elements into a small lateral footprint, reducing device dimensions while maintaining manufacturability through vertical integration rather than lateral proliferation.
3Area of stationary object
If the distance between adjacent nanosheet stacks is reduced to shrink device size, then device area is reduced, but patterning window becomes constrained
Solution Approach 1:
The patent resolves the patterning constraint by moving the separation function to the vertical dimension through dummy spacers, allowing lateral features to be formed with relaxed pitch requirements. This enables reduced device area while maintaining adequate patterning windows, as the critical spacing is achieved vertically rather than laterally where lithography resolution limits apply.
Solution Approach 2:
The patent introduces dummy spacers as intermediary structures between adjacent nanosheet stacks of the same type. These dummy spacers act as mediators that provide the necessary electrical isolation and spacing without requiring tight lateral patterning, thus enabling reduced device area while preserving the patterning window by performing the spacing function in a non-critical lateral dimension.
4Manufacturing precision
If dummy spacers are used to separate same-type metal gates and epitaxial source/drain features, then overlay shifting issues are mitigated, but device structure becomes more complex
Solution Approach 1:
The patent uses dummy spacers as intermediary structures that provide overlay alignment references during fabrication. These dummy features serve as mediators between the lithography process and the actual device structures, enabling precise overlay by providing visible alignment markers without becoming part of the final functional device, thus mitigating overlay shifting while adding minimal structural complexity.
Solution Approach 2:
The patent employs dummy spacers that are formed during fabrication to provide alignment and spacing functions, then selectively removed in subsequent processing steps. These temporary structures are discarded after serving their alignment purpose, allowing the achievement of high manufacturing precision for overlay alignment without permanent addition to the device structure, thus minimizing the impact on device complexity.
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.