Fishbone Power Network Layout for Routing Resource Optimization

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Solution Overview

Problem

In advanced technology nodes, the wide metal spacing rule in power networks of integrated circuit chips leads to insufficient routing resources, causing routing detours and performance issues due to the blocking of adjacent routing tracks by conductive lines with wide widths, which affects the density and efficiency of the power network.

Innovation Solution

The implementation of a fishbone structure with conductive segments and interlayer vias that do not trigger the wide metal spacing rule, allowing for routing tracks adjacent to conductive lines to be available by optimizing the width and orientation of conductive segments in relation to overlapping layers, thereby avoiding the rule's constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If conductive lines with wide widths are used in power networks, then current carrying capacity is improved, but routing resources are blocked causing routing detours

Engineering Contradiction:
Improvecurrent carrying capacityVSAvoidrouting resource availability
Core Design Contradiction:
PowerVSEase of operation

Solution Approach 1:

The patent applies dimensionality change by transitioning from a two-dimensional planar layout to a three-dimensional stacked configuration. Conductive segments are arranged in multiple layers (first conductive layer, second conductive layer) with vertical interconnections via vias. This allows current paths to extend in the vertical dimension, increasing current carrying capacity without blocking horizontal routing tracks in any single layer, thus resolving the contradiction between power capacity and routing availability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the continuous conductive lines into discrete conductive segments arranged in a fishbone pattern. The conductive segments in the first layer are interrupted and connected to corresponding segments in the second layer through vias. This segmentation allows routing tracks to pass through the gaps between segments, maintaining routing resource availability while the stacked segmented structure provides enhanced current carrying capacity through multiple parallel paths.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If wide metal spacing rule is applied, then manufacturing precision is improved, but power network density decreases

Engineering Contradiction:
Improvespacing controlVSAvoidpower network density
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The patent resolves the spacing-density contradiction by utilizing the vertical dimension. Instead of increasing horizontal spacing to satisfy manufacturing rules, the design stacks conductive segments in multiple layers with controlled vertical spacing. This allows tight horizontal spacing (maintaining high density) while using the vertical separation between layers to satisfy manufacturing precision requirements for spacing control.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where conductive segments in the second layer are positioned to overlap with or interleave with segments in the first layer, forming a compact fishbone pattern. This nesting allows the power network to achieve high density by efficiently utilizing vertical space, while the controlled spacing between nested layers satisfies manufacturing precision requirements.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS20220139826A1Fishbone structure enhancing spacing with adjacent conductive line in power network
Publication Date: 2022.05.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20220139826A1 patent drawing
  • US20220139826A1 patent drawing
  • US20220139826A1 patent drawing

AI summary

A method of generating a power network layout is provided. A first conductive line, generated by a processor, is in a first conductive layer along a first direction. A plurality of second conductive lines, generated by a processor, is in a second conductive layer along a second direction, substantially vertical to the first direction. The second conductive lines overlap with the first conductive line. A first plurality of interlayer vias, generated by a processor, is interposed between the first conductive layer and the second conductive layer at where the second conductive lines overlapping the first conductive line. Each of the second conductive lines has a width such that a first routing track adjacent to the first conductive line is available for routing or a second routing track adjacent to one of the plurality of second conductive lines is available for routing.