Five Level Cell Program Algorithm With Bit Level Erase
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Solution Overview
Problem
Existing non-volatile memory devices face challenges in maintaining the integrity of threshold voltage distributions during programming operations, particularly in advanced multi-level-cell technologies like quad-level cells (QLC) and five-level cells (PLC), which suffer from increased program disturb and reduced threshold voltage budget.
Innovation Solution
A memory apparatus and method that includes memory cells connected to word lines, with a control means applying programming pulses of a program voltage to selected word lines during programming loops and reducing the threshold voltage of memory cells targeted for an erased state during a bit-level erase operation following programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If programming operations are performed on memory cells in advanced multi-level-cell technologies (QLC and PLC), then storage capacity is improved, but program disturb increases and threshold voltage budget is reduced
Solution Approach 1:
The patent segments the memory cell population into two distinct groups: memory cells targeted for erasure and memory cells targeted for programming. By applying different voltage operations to different segments of the memory array simultaneously, the patent achieves parallel processing that reduces overall operation time while preventing program disturb in cells not targeted for programming. This segmentation allows QLC and PLC memory devices to maintain reliability while improving storage capacity utilization.
Solution Approach 2:
The patent performs a preliminary determination of which memory cells should be erased and which should be programmed before executing the actual operations. By pre-identifying the target cells and applying appropriate voltages in advance, the system prepares the memory cells for their respective operations, ensuring that cells not targeted for programming are protected from program disturb while cells targeted for programming receive the necessary programming voltage.
2Quantity of substance
If programming operations are performed on memory cells, then data storage is improved, but some memory cells are disturbed during programming
Solution Approach 1:
The patent applies different voltage conditions to different spatial locations within the memory array. Memory cells targeted for erasure receive erase voltages while maintaining programming protection, whereas memory cells targeted for programming receive programming voltages. This localized differentiation of voltage application ensures that each cell receives only the operation it requires, preventing program disturb in cells that should remain unchanged while enabling efficient data storage in target cells.
3Reliability
If bit-level erase operation is applied following programming, then threshold voltage budget is improved and reliability is enhanced, but operation time increases
Solution Approach 1:
The patent merges the erase operation and programming operation into a single unified process that occurs simultaneously in different segments of the memory array. By combining these operations that traditionally would be performed sequentially into a parallel execution model, the patent achieves the threshold voltage budget improvements of bit-level erase while avoiding the time penalty of sequential execution. This merging of operations maintains reliability enhancement without significant increase in total operation time.
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage. A control means is coupled to the plurality of word lines and is configured to apply at least one programming pulse of a program voltage to selected ones of the plurality of word lines during at least one programming loop of a programming operation. The control means is also configured to reduce the threshold voltage of the memory cells targeted for an erased state during a bit-level erase operation following the programming operation.