Five-Transistor Bit Cell Memory with Shared Power Control
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Solution Overview
Problem
Reconfigurable circuits, such as FPGA devices, face challenges with large memory bit cell designs due to the use of six-transistor bit cells, which occupy excessive space and complicate the metal layers, limiting the number of dedicated metal layers for memory planes.
Innovation Solution
The implementation of five-transistor bit cells with a bi-stable loop and a single access transistor, along with a controller that manages power supply to reduce the size of memory bit cells and improve routability, using a power supply control circuit to control reading and writing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If six-transistor bit cells are used in memory blocks, then memory functionality is achieved, but the surface area occupied is excessive and metal layers become crowded
Solution Approach 1:
The patent extracts the power supply control function from individual bit cells and implements it at the memory block level through a shared controller. This removes redundant transistors from each bit cell, reducing the area per bit cell while maintaining memory functionality through the centralized power management approach.
Solution Approach 2:
The controller circuit serves multiple functions: it controls power supply to multiple bit cells simultaneously, manages read/write operations across the memory block, and coordinates access to multiple bit lines. This multi-functionality reduces the need for dedicated control circuitry in each bit cell, thereby reducing overall area.
2Reliability
If six-transistor bit cells are used in memory blocks, then memory operations are performed, but the number of metal layers required increases
Solution Approach 1:
The patent merges the power control functionality into a shared controller that manages multiple bit cells. By combining control functions at the block level rather than implementing them in each individual bit cell, the design reduces the number of required metal layers while maintaining full memory operation capability.
3Area of stationary object
If five-transistor bit cells are used, then the area of configuration memory is reduced, but power supply control complexity increases
Solution Approach 1:
The patent shifts the power control dimension from the bit cell level to the memory block level. By implementing power supply control in the temporal dimension (through a controller that manages power timing) rather than the spatial dimension (through individual bit cell transistors), the design reduces area while managing complexity through centralized control.
Data Source
AI summary
Memory employing a plurality of five-transistor memory bit cells in a memory matrix and a power supply control circuit that is configured to provide a simultaneous full clear to all of the memory bit cells is described herein.