Five-Transistor XOR Circuit Layout for Low-Voltage Logic
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Solution Overview
Problem
Conventional exclusive OR circuits in semiconductor design are inefficient due to a large number of transistors, leading to increased chip area and delayed data processing, particularly in low-voltage, high-integration, and small-size semiconductor apparatuses.
Innovation Solution
The exclusive OR circuit is redesigned with a low pass unit, a high pass unit, and a discharge unit, utilizing CMOS transistors to manage data flow and voltage levels, where the low pass unit applies data based on input levels and the discharge unit controls the output node voltage, optimizing transistor usage and data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional exclusive OR circuit is designed using multiple logic gates (OR gate, NAND gate, AND gate), then the circuit can perform the exclusive OR logic operation, but the number of transistors increases, leading to increased chip area and reduced design efficiency
Solution Approach 1:
The patent merges multiple logic gate functions into a unified circuit structure using only five transistors. The low pass unit, high pass unit, and discharge unit are integrated to perform the exclusive OR operation simultaneously, eliminating the need for separate OR, NAND, and AND gates. This consolidation reduces the transistor count from the conventional design to just five transistors while maintaining the exclusive OR logic functionality.
Solution Approach 2:
The circuit is segmented into three functional units: a low pass unit (first and second transistors) that applies data based on input levels, a high pass unit (third and fourth transistors) that generates discharge signals, and a discharge unit (fifth transistor) that controls output voltage. This segmentation allows each unit to perform a specific function with minimal transistors, achieving the exclusive OR operation efficiently.
2Reliability
If the conventional exclusive OR circuit structure is used, then the logic operation can be performed, but the chip area increases due to the large number of transistors required
Solution Approach 1:
Multiple logic gate functions are merged into a single integrated circuit structure using five transistors. The low pass unit, high pass unit, and discharge unit share common components and operate in coordination, reducing the total transistor count and consequently minimizing the chip area required for the exclusive OR operation.
Solution Approach 2:
Each transistor in the circuit serves multiple functions. For example, the first transistor acts as a switch in the low pass unit while also contributing to the overall logic operation. This multi-functionality reduces the total number of transistors needed, thereby reducing chip area.
3Reliability
If more transistors are used in the exclusive OR circuit, then the logic operation can be implemented, but the data processing time is delayed
Solution Approach 1:
The circuit merges the functions of multiple logic gates into a single streamlined structure with five transistors. This reduces the number of sequential operations required to perform the exclusive OR logic, thereby decreasing the data processing time while maintaining operational accuracy.
Solution Approach 2:
The low pass unit and high pass unit are configured to prepare data and generate discharge signals in advance, so that when the exclusive OR operation is needed, the circuit can respond quickly. This preliminary preparation of data paths and control signals reduces the overall processing time.
Data Source
AI summary
An exclusive OR circuit includes, inter alia: a low pass unit configured to apply a second data to an output node when a first data is at a low level and to apply the first data to the output node when the second data is at a low level, and a discharge unit configured to discharge a voltage level of the output node when the first and second data are at a high level.