Parallel Data Transmitter Using Fixed Data During HiZ Switching

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Solution Overview

Problem

In semiconductor integrated circuits, power-supply noise amplification on signal lines between data transmitting and receiving circuits impairs accurate data transmission, particularly when data output circuits switch from high impedance mode to data transmission mode.

Innovation Solution

A semiconductor integrated circuit design that includes data output circuits capable of outputting fixed data during the transition period from high impedance mode to data transmission mode, using a control circuit to manage the output and reduce noise amplification by selecting and outputting either transmission data or pre-set fixed data on signal lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data output circuits switch from high impedance mode to data transmission mode simultaneously, then data transmission speed is improved, but power-supply noise amplification occurs and data transmission accuracy deteriorates

Engineering Contradiction:
Improvedata transmission speedVSAvoiddata transmission accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by having data output circuits output fixed data (different from actual transmission data) before switching to data transmission mode. This preliminary output of fixed data prevents simultaneous switching of all circuits, thereby reducing power-supply noise amplification while maintaining fast data transmission speed. The fixed data is output during a predetermined period before the actual data transmission begins.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If data output circuits output biased data with H or L level voltage, then data output capability is maintained, but power-supply noise is amplified and data transmission accuracy deteriorates

Engineering Contradiction:
Improvedata output capabilityVSAvoiddata transmission accuracy
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies parameter changes by altering the output data value during the transition period. Instead of outputting biased data with H or L level voltage that causes noise amplification, the circuit outputs fixed data with a different voltage level during the predetermined period before data transmission. This parameter change in the output data prevents power-supply noise amplification while maintaining the data output capability of the circuits.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If ODT function is used to reduce power-supply noise on signal lines, then data receiving circuit performance is improved, but no countermeasure is provided for data transmitting circuit noise

Engineering Contradiction:
Improvedata receiving circuit performanceVSAvoidnoise reduction coverage
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies segmentation by dividing the noise reduction approach into two parts: the ODT function for the data receiving circuit and the fixed data output mechanism for the data transmitting circuit. This segmentation allows each circuit to have its own targeted noise reduction measure, providing comprehensive coverage for both transmitting and receiving operations while maintaining high reliability for both circuits.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7999572B2Semiconductor integrated circuit
Publication Date: 2011.08.16 RENESAS ELECTRONICS CORP
  • US7999572B2 patent drawing
  • US7999572B2 patent drawing
  • US7999572B2 patent drawing

AI summary

Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit that transmits data in parallel through a plurality of signal lines and a data receiving circuit that receives the data. The data transmitting circuit includes a plurality of data output circuits that output the data in a data transmission mode or set an output to a high impedance state in a HiZ mode, a plurality of data selection circuits that select one of the data and fixed data and output the selected data to the data output circuits, and a control circuit that controls the data output circuits to output the fixed data during a period between a time when a mode is switched from the HiZ mode to the data transmission mode and a time when the data output circuits start to output the data.