Fixed-Length Symbol Encoding Without VLC Buffers

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Solution Overview

Problem

Existing codecs for encoding and decoding data sequences, such as video or audio, require significant hardware resources due to the use of variable length codes (VLC) and FIFO buffers, leading to increased hardware cost and complexity, especially when dealing with short bursts of encoded data that are larger than the source data.

Innovation Solution

A method and system that utilize a predetermined set of transformations to map symbols of a first data type to a second data type with different code lengths, incorporating both lossless and lossy transformations, allowing for efficient encoding and decoding without the need for VLC buffers, by determining the appropriate transformation based on the previous symbol in the sequence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If variable length codes (VLC) are used for data compression, then data compression efficiency is improved, but hardware resource requirements increase due to the need for VLC data buffers

Engineering Contradiction:
Improvedata compression efficiencyVSAvoidhardware resource requirements
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts and removes the VLC data buffer component from the encoding system. By using fixed length codes instead of variable length codes, the system eliminates the need for FIFO buffers that were required to handle variable code lengths, thereby reducing hardware resources while maintaining compression functionality through the predetermined transformation sets

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the code length parameter from variable to fixed. By transforming the encoding scheme from VLC to fixed length codes with predetermined transformation sets, the system achieves compression without requiring dynamic buffer management, thus reducing hardware complexity while preserving productivity

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If pixel prediction algorithm is used to achieve light compression with small hardware size, then hardware cost is reduced, but the encoded data still produces short bursts larger than source data requiring FIFO buffers

Engineering Contradiction:
Improvehardware sizeVSAvoidencoded data size
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent applies preliminary action by pre-defining multiple transformation sets that map source symbols to encoded symbols with different code lengths. These transformation sets are determined in advance based on statistical properties, allowing the system to handle data size variations without requiring runtime buffer adjustments or FIFO structures

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces dynamics by allowing the selection of different predetermined transformation sets based on the characteristics of the data being encoded. This dynamic selection approach enables the system to adapt to different data patterns while maintaining fixed length coding, thus reducing both hardware size and encoded data size without requiring FIFO buffers

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250317156A1Encoding method and system
Publication Date: 2025.10.09 BLACKMAGIC DESIGN PTY LTD
  • US20250317156A1 patent drawing
  • US20250317156A1 patent drawing
  • US20250317156A1 patent drawing

AI summary

Disclosed herein are methods of transforming an nth symbol of a first data sequence into an mth symbol of a second data sequence. Also disclosed is a method of decoding an mth symbol of a second data sequence having a second data type and being created by encoding the nth symbol of a first data sequence having a first data type, said decoding generating an output symbol having said first data type. There is also disclosed encoding and decoding devices. For example, the encoding device comprises an input on which a first data sequence is received, an output on which a second data sequence is transmitted and a processing system configured to process received symbols of the first data sequence in series and output symbols of the second data sequence.