Fixed-Point Floating-Point Adder for One-Cycle Accumulation

Solution Overview

Problem

Existing floating-point adders face long path delays due to the need for digit alignment and normalization in floating-point addition operations, which slows down the processing of high-dimensional vector dot products essential for image recognition, leading to reduced system performance.

Innovation Solution

A floating-point adder configuration that converts operands into fixed-point numbers for addition/subtraction, eliminating the need for digit alignment and normalization, allowing for faster processing by performing these operations in one cycle without shift operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If floating-point addition is performed using conventional methods with digit alignment and normalization, then the addition operation can handle floating-point numbers with large dynamic range, but the path delay becomes long and processing speed decreases

Engineering Contradiction:

Improveprocessing speedVSAvoidpath delay

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent changes the numerical representation parameter from floating-point to fixed-point during the addition operation. By converting floating-point operands to fixed-point format, the system eliminates the need for digit alignment and normalization operations, thereby reducing path delay and improving processing speed. After the addition, the result is converted back to floating-point format.

Inventive Principle:

Principle #35Parameter changes

2Productivity

If floating-point addition requires digit alignment and normalization operations, then accurate floating-point arithmetic can be achieved, but the operation cannot be completed in one cycle

Engineering Contradiction:

Improveoperation throughputVSAvoidoperation cycle time

Core Design Contradiction:

ProductivityVSDuration of action of moving object

Solution Approach 1:

The patent changes the numerical representation parameter from floating-point to fixed-point during the addition operation. By converting floating-point operands to fixed-point format, the system eliminates the need for digit alignment and normalization operations, thereby reducing path delay and improving processing speed. After the addition, the result is converted back to floating-point format.

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If a shifter is used for digit alignment in floating-point addition, then correct alignment of mantissas can be achieved, but the device complexity and path delay increase

Engineering Contradiction:

Improvealignment precisionVSAvoidadder structure complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent changes the numerical representation parameter from floating-point to fixed-point during the addition operation. By converting floating-point operands to fixed-point format, the system eliminates the need for digit alignment and normalization operations, thereby reducing path delay and improving processing speed. After the addition, the result is converted back to floating-point format.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent extracts and removes the shifter component from the floating-point adder structure by converting to fixed-point arithmetic. This elimination of the shifter reduces device complexity and path delay while maintaining addition accuracy through the fixed-point representation system.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS10340944B2Floating-point adder, semiconductor device, and control method for floating-point adder

Publication Date: 2019.07.02 RENESAS ELECTRONICS CORP

AI summary

An object of the invention is to speed up processing of adding floating-point numbers. A floating-point adder includes: a first register configured to store a first fixed-point number having a predetermined number of digits corresponding to a result of accumulation of a plurality of floating-point numbers; a first conversion unit configured to convert an input first floating-point number into a second fixed-point number having the predetermined number of digits; a second register configured to store the second fixed-point number; an adder configured to add the second fixed-point number stored in the second register and the first fixed-point number stored in the first register, and store a result of the addition in the first register as the first fixed-point number; and a second conversion unit configured to convert the first fixed-point number into a second floating-point number, and output the second floating-point number.