Fixed-Point Arithmetic Optimization for Quantization Error Cancellation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing quantization methods in digital processing systems, such as truncation and rounding, introduce additive or non-canceling errors in calculations, leading to inaccuracies and increased hardware requirements.
Innovation Solution
Implementing a double sign inversion truncation (DIT) operation to pair sub-sets of arithmetic operations with comparable truncation errors, canceling these errors and reducing hardware overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If truncation is used to quantize decimal fractions to fixed length binary numbers, then hardware cost and processing penalties are reduced, but truncation errors accumulate additively across multiple arithmetic operations
Solution Approach 1:
The patent divides the arithmetic operations into two distinct sub-sets: a first sub-set processed using conventional truncation and a second sub-set processed using double sign inversion truncation. This segmentation allows each sub-set to have complementary error characteristics that cancel each other out, resolving the contradiction between hardware simplicity and calculation accuracy.
Solution Approach 2:
The patent changes the parameter of the truncation operation by introducing a double sign inversion process for the second sub-set. This parameter change transforms the error distribution from purely additive (conventional truncation) to canceling (double sign inversion truncation), achieving zero-mean error without requiring additional hardware complexity.
2Measurement precision
If rounding is used to quantize decimal fractions, then mean average error is minimized to zero, but additional arithmetic operations and hardware elements are required
Solution Approach 1:
Instead of using expensive rounding operations that require additional hardware elements like extra adders, the patent employs a cheaper double sign inversion truncation method. This method achieves zero-mean error through a simple sign inversion and truncation process that can be implemented with existing hardware resources, effectively replacing the need for costly rounding circuits.
3Measurement precision
If rounding operations are applied to all arithmetic operations, then truncation errors cancel out, but computational penalty increases due to additional arithmetic operations
Solution Approach 1:
The patent segments the arithmetic operations into two sub-sets with different processing methods. The first sub-set uses fast conventional truncation while the second sub-set uses double sign inversion truncation. This segmentation allows the system to achieve error cancellation without applying the computationally expensive rounding operation to all operations, thereby maintaining high computational efficiency.
Solution Approach 2:
Instead of applying rounding (or double sign inversion truncation) to all arithmetic operations, the patent applies the more complex double sign inversion truncation only to the second sub-set of operations. This partial application is sufficient to achieve zero-mean error cancellation while minimizing the computational penalty, as only a portion of the operations require the enhanced error cancellation.
Data Source
AI summary
There are provided systems and methods for reducing quantization errors, including method of optimizing a routine for a hardware-based processing system having a fixed length two's complement binary representation, the method comprising: receiving an instruction sequence arranged to perform the routine, wherein the instruction sequence comprises a set of arithmetic operations, wherein the outputs of the arithmetic operations exceed a precision of the hardware-based processing system; identifying one or more pairs of sub-sets of instructions in the sequence of instructions, the sub-sets of each pair having a respective comparable truncation error; and generating an optimized routine by modifying one of the sub-sets of each pair to invert the sign of one or more inputs to said sub-sets and modifying the instruction sequence to compensate for the said inversion.