Fixed-Point ML Processor Architecture for Large-Load Computation
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Solution Overview
Problem
General purpose processors are inefficient in processing large loads, leading to delays in machine learning tasks such as training artificial intelligence models, due to their limited operating speed.
Innovation Solution
A computation device and method that includes a controller unit, operation unit, and conversion unit, utilizing a primary processing circuit and secondary processing circuits to perform machine learning computations by converting input data into fixed-point data and executing operations to improve processing speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a general purpose processor is used to process information, then the processor can handle various types of computations, but the processing speed becomes limited and efficiency decreases when dealing with large loads
Solution Approach 1:
The processor is divided into a control unit and multiple operation units. The control unit parses computation instructions and generates operation instructions, while the operation units execute specific computations in parallel. This segmentation allows the system to maintain versatility through the control unit's instruction parsing capability while achieving high processing speed through parallel execution in multiple operation units.
Solution Approach 2:
The patent transitions from sequential single-processor operation to parallel multi-unit operation by adding a temporal dimension. The control unit operates in the instruction generation dimension while multiple operation units operate simultaneously in the computation execution dimension, effectively increasing processing throughput without sacrificing adaptability.
2Productivity
If a general purpose processor operates at high speed, then processing efficiency improves, but the processor architecture becomes complex and difficult to optimize for specific tasks
Solution Approach 1:
The processor architecture is segmented into a control unit responsible for instruction parsing and generation, and multiple operation units responsible for execution. This clear functional segmentation simplifies the overall architecture by separating control logic from execution logic, making each unit simpler and more optimized for its specific function while maintaining high processing efficiency through parallel execution.
Solution Approach 2:
The processor employs dynamic instruction generation where the control unit parses computation instructions and generates appropriate operation instructions based on the specific task requirements. This dynamic approach allows the system to optimize for different tasks without requiring a completely different architecture, maintaining simplicity while achieving high efficiency for specific computations.
3Speed
If more processing units are added to increase parallel processing capability, then computation speed improves, but the device complexity and resource requirements increase
Solution Approach 1:
The system is segmented into one control unit and multiple operation units with clearly defined roles. The control unit handles instruction parsing and generation, while operation units handle execution. This segmentation allows parallel processing to speed up computation without proportionally increasing overall system complexity, as the control unit remains singular and manages all operation units centrally.
Solution Approach 2:
Multiple operation units are designed with universal functionality to execute different types of computations. Each operation unit can perform various operations based on the instructions received from the control unit, reducing the need for specialized hardware for each computation type. This multi-functionality increases computation speed through parallel execution while keeping device complexity manageable through standardized unit design.
Data Source
AI summary
The present disclosure provides a computation device. The computation device is configured to perform a machine learning computation, and includes an operation unit, a controller unit, and a conversion unit. The storage unit is configured to obtain input data and a computation instruction. The controller unit is configured to extract and parse the computation instruction from the storage unit to obtain one or more operation instructions, and to send the one or more operation instructions and the input data to the operation unit. The operation unit is configured to perform operations on the input data according to one or more operation instructions to obtain a computation result of the computation instruction. In the examples of the present disclosure, the input data involved in machine learning computations is represented by fixed-point data, thereby improving the processing speed and efficiency of training operations.