Fixed-Point Polynomial Hardware Logic Error Distribution
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Solution Overview
Problem
Existing methods for implementing fixed-point polynomials in hardware logic are inefficient in terms of resource usage and do not guarantee bounded error, lacking a systematic approach to distribute and optimize error across operators in a data-flow graph.
Innovation Solution
The method optimizes the distribution of a user-defined maximum absolute error across operators in a data-flow graph by defining error in terms of precision and accuracy parameters, allowing for reduced resource usage and guaranteed error bounds, resulting in a hardware representation that minimizes area and power consumption while maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing methods for implementing fixed-point polynomials in hardware logic are used, then the implementation can be achieved, but resource usage is inefficient and error bounds are not guaranteed
Solution Approach 1:
The patent changes the parameters of the hardware implementation by distributing a user-defined maximum absolute error across operators in the data-flow graph. By defining error in terms of precision and accuracy parameters and optimizing each operator to satisfy allocated error portions, the system achieves guaranteed error bounds while reducing hardware resource usage through systematic error distribution and optimization.
2Area of stationary object
If hardware logic is optimized for reduced resource usage, then area and power consumption decrease, but error bounds may not be guaranteed
Solution Approach 1:
The patent implements a feedback mechanism where the error distribution is optimized iteratively. The system distributes the maximum absolute error across operators, updates the distribution in an iterative process until a stop condition is reached, and ensures that each operator is optimized to satisfy its allocated error portion. This feedback loop guarantees error bounds while achieving reduced hardware area.
3Reliability
If iterative error distribution optimization is performed, then error bounds are guaranteed, but the time to generate hardware logic increases
Solution Approach 1:
The patent applies preliminary action by distributing the error bound before detailed hardware optimization. By first allocating error portions to each operator in the data-flow graph and then optimizing each operator to satisfy its allocated error, the system reduces the complexity of the iterative process and accelerates hardware generation time while maintaining error bound guarantees.
Data Source
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AI summary
Methods of implementing fixed-point polynomials in hardware logic are described. In an embodiment the method comprises distributing a defined error bound for the whole polynomial between operators in a data-flow graph for the polynomial by solving an optimization problem which outputs an accuracy parameter and a precision parameter for each node. Each operator is then itself optimized to satisfy the part of the error bound allocated to that operator and as defined by the accuracy and precision parameters. To be accompanied, when published, by Figure 3 of the accompanying drawings.