Fixed-Point Arithmetic Sign Inversion for Quantization Error Cancellation
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Solution Overview
Problem
Existing quantization methods in digital processing systems, such as truncation and rounding, introduce significant errors in calculations due to fixed bit precision, leading to inefficiencies and hardware overheads.
Innovation Solution
Implementing a double sign inversion truncation (DIT) operation to cancel truncation errors by inverting the sign of input values in pairs of arithmetic operations, reducing hardware requirements and maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If rounding schemes are used to minimize quantization error, then measurement precision is improved, but device complexity increases due to additional arithmetic operations and hardware elements
Solution Approach 1:
The patent applies sign inversion to the input values before truncation operations. By inverting the sign of input values in pairs of arithmetic operations and then compensating for the inversion, the patent transforms the harmful truncation error into a beneficial error cancellation mechanism, achieving zero mean error without requiring complex rounding hardware
2Device complexity
If truncation is used to reduce hardware cost, then device complexity is reduced, but measurement precision deteriorates due to additive errors
Solution Approach 1:
The patent converts the harmful truncation error into a beneficial feature by applying sign inversion to pairs of operations. The truncation errors that would normally accumulate additively are transformed to cancel each other out, achieving zero mean error while maintaining the simplicity of truncation hardware
3Measurement precision
If rounding operations are applied to reduce quantization error, then measurement precision is improved, but productivity decreases due to additional computational overhead
Solution Approach 1:
The patent replaces computationally expensive rounding operations with simpler truncation operations combined with sign inversion. By inverting signs of input values in pairs and compensating for the inversion, the patent achieves the same error cancellation effect as rounding but with significantly reduced computational overhead
Data Source
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AI summary
There are provided systems and methods for reducing quantization errors, including method of optimizing a routine for a hardware-based processing system having a fixed length two's complement binary representation, the method comprising: receiving an instruction sequence arranged to perform the routine, wherein the instruction sequence comprises a set of arithmetic operations, wherein the outputs of the arithmetic operations exceed a precision of the hardware-based processing system; identifying one or more pairs of sub-sets of instructions in the sequence of instructions, the sub-sets of each pair having a respective comparable truncation error; generating an optimized routine by modifying one of the sub-sets of each pair to invert the sign of one or more inputs to said sub-sets, and modifying the instruction sequence to compensate for the said inversion.