Fixed-Rate SerDes for Bad Column Management in Non-Volatile Memory
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Solution Overview
Problem
The existing semiconductor memory systems face limitations in data transfer rates due to the serialization/deserialization process between serial and parallel formats, which can be slowed down by defective columns in memory arrays, leading to variable cycle rates and increased complexity as clock rates increase.
Innovation Solution
The memory array is divided into M+N divisions, allowing up to N defective columns to be accommodated while maintaining a fixed rate for serialization and deserialization, using a skip mechanism for write data and multiplexing for read data to avoid bad columns, enabling efficient data transfer with relaxed timing requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred serially at high data rates between latches and memory cells, then data transfer speed is improved, but timing requirements at data latches become more stringent and complex
Solution Approach 1:
The memory array is divided into multiple divisions (e.g., 8 divisions), allowing parallel data transfer across multiple channels. This segmentation enables the system to maintain high data transfer rates while distributing the timing complexity across multiple simpler parallel paths, reducing the burden on individual serialization/deserialization circuits.
2Reliability
If the memory array is accessed with variable cycle rates to accommodate defective columns, then reliability is improved, but device complexity and timing management become more difficult
Solution Approach 1:
Defective columns are identified and marked during manufacturing testing before the memory device is deployed. This preliminary identification allows the system to pre-configure skip mechanisms and redundancy mappings, enabling reliable accommodation of defective columns without requiring complex real-time detection and adaptation during operation.
Solution Approach 2:
Redundant columns and intermediate mapping circuits serve as mediators between the defective columns and the functional memory array. These intermediaries allow the system to bypass defective columns while maintaining uniform cycle rates, preventing the propagation of timing complexity throughout the memory system.
3Productivity
If parallel data transfer is used across multiple divisions, then data transfer efficiency is improved, but the impact of defective columns on overall transfer rate increases
Solution Approach 1:
Each division within the memory array is independently configured with its own set of redundant columns and skip mechanisms. This local quality approach ensures that a defective column in one division does not impact the operational status of other divisions, allowing parallel data transfer to continue at full efficiency across healthy divisions while isolating the impact of defects to minimal local areas.
Data Source
AI summary
In a non-volatile memory circuit, performance is improved by converting data between a serial format, for transfer on and off of the memory circuit, and a parallel format, for transfer to and from the memory latches used for read and writing data into the memory array of the memory circuit. The memory array is split into M+N divisions, but transferred with a degree of parallelism of M, allowing M words of data to be transferred in parallel at a fixed transfer rate while allowing for up to N bad columns in a transfer. In the write path, a column skipping mechanism is used when converting words of write data into a parallel format. In the read path, a set of (M+N) to 1 multiplexers is used to align the word of read data so that read data can be transferred at a fixed rate and without any added latency.