Fixed-Token Data Compression for FPGA and ASIC Throughput

The patent segments the compressed data stream into distinct token types (literal tokens, match tokens, repeat tokens) with fixed-length encoding. Each token is processed independently through dedicated hardware modules, enabling parallel processing and eliminating the sequential bottlenecks present in traditional LZ algorithms. This segmentation allows the system to achieve high compression ratios while maintaining constant-time processing for each token.

The patent changes the fundamental parameters of the compression algorithm by using fixed-length token encoding instead of variable-length encoding, and by introducing a minimum match length parameter (minMatch) that optimizes the balance between compression ratio and processing speed. These parameter changes enable the algorithm to be efficiently implemented in hardware with predictable timing characteristics.

The patent replaces the mechanical system of general-purpose CPU execution with a dedicated hardware architecture implemented in FPGA or ASIC. The compression algorithm is hardwired into the hardware logic, with dedicated modules for hash calculation, match searching, token generation, and output assembly. This substitution eliminates the overhead of instruction fetching, decoding, and control flow management, achieving significant speedups while maintaining algorithmic flexibility through configurable parameters.

The patent creates a universal hardware compression engine that can handle various data types and compression requirements through configurable parameters such as hash table size, minMatch length, and token encoding format. The same hardware architecture can be adapted to different applications by adjusting these parameters, providing both hardware efficiency and algorithmic versatility.

The patent segments the encoding into fixed-length tokens where each token type (literal, match, repeat) has a predetermined bit length. This segmentation eliminates the need for variable-length decoding logic, allowing the decoder to simply read fixed-number-of-bits tokens in sequence and reconstruct the original data without complex parsing or state management.

Instead of using variable-length encoding to achieve compression (where longer sequences require more bits), the patent inverts the approach by using fixed-length encoding where each token represents a fixed amount of information. The compression is achieved not through variable-length representation but through the statistical frequency of different token types and the efficiency of the fixed-length representation in capturing data redundancy.