Fixed-Width ECC Input Circuits for Multi-Mode Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in accommodating different numbers of bits accessed during operations without altering the logic tree of the ECC circuit, as they operate in various modes with varying input bit requirements.
Innovation Solution
The implementation of an ECC input circuit that generates filler bits to adjust the variable number of input bits to a fixed number expected by the ECC engine, ensuring consistent operation across different modes by maintaining a fixed input for the ECC engine, regardless of the varying bit requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the ECC circuit is designed with a fixed logic tree for a specific number of input bits, then the error correction functionality is reliable and precise, but the device cannot accommodate different operational modes with varying bit requirements
Solution Approach 1:
The patent applies dynamics by making the ECC circuit configurable through select signals that dynamically adjust the logic tree configuration. The select signals enable or disable specific logic paths based on the operational mode, allowing the same physical circuit to adapt to different bit requirements without physical reconfiguration.
Solution Approach 2:
The patent changes the operational parameters of the ECC circuit by using select signals to modify which logic paths are active. This allows the circuit to handle different numbers of data bits and parity bits by changing the effective configuration of the logic tree through signal control rather than physical restructuring.
2Adaptability or versatility
If the ECC circuit logic tree is reconfigured for each operational mode, then the circuit can handle varying bit requirements, but the device complexity and reconfiguration overhead increase
Solution Approach 1:
The patent implements preliminary action by pre-configuring multiple logic paths within the ECC circuit that can be selectively activated. The select signals are prepared in advance to enable the appropriate pre-existing logic configuration, eliminating the need for dynamic reconfiguration during operation and simplifying the operational process.
3Stability of the object's composition
If filler bits are added to match the expected input count, then the ECC engine receives consistent input, but additional circuit logic is required to manage the filler bits
Solution Approach 1:
The patent merges the filler bit generation logic with the existing ECC logic tree structure. The select signals that control the logic tree configuration also manage the filler bit insertion, combining multiple functions into a unified control mechanism that reduces overall circuit complexity while maintaining stable input composition.
Data Source
AI summary
Apparatuses, systems, and methods for variable input error correction code (ECC) circuits. Different modes of a memory device may involve different numbers of bits of information (e.g., data and/or metadata) being accessed. An ECC input circuit receives the variable number of bits of information and provides a fixed number of input bits. An ECC engine uses the input bits to generate parity (during a write) or to locate errors (during a read). The number of input bits may be based on a number of inputs of the ECC engine. The ECC input circuit may generate filler bits to add to the bits of information to generate the input bits.