Fixed-Width Pulse Generator for PVT-Stable Secure Timing
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Solution Overview
Problem
Conventional fixed-width pulse generators in SoCs face issues with pulse width variability due to process, voltage, and temperature variations, potentially compromising security by requiring external or internal clock signals and leading to leakage of secure information.
Innovation Solution
A fixed-width pulse generator incorporating a metastability detector circuit, delay signal generator, and combinational logic circuit that delays a trigger signal by different values based on state detection signals to generate a constant pulse width, eliminating the need for external or internal clock signals and compensating for PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external reference clock signal is used to generate the pulse signal, then the pulse width can be maintained, but secure information may be leaked
Solution Approach 1:
The patent extracts and eliminates the external reference clock signal from the pulse generation system. Instead of using an external clock, the invention uses only the trigger signal and internal delay circuits to generate the pulse, thereby removing the security vulnerability while maintaining pulse width constancy through PVT-compensated delay elements
Solution Approach 2:
The patent introduces delay elements and compensation circuits as intermediaries between the trigger signal and the output pulse. These intermediate components (delay elements, adder circuit, compensation logic) process the trigger signal to generate a constant-width pulse without requiring external clock references, thus maintaining reliability while ensuring security
2Loss of information
If an internal reference clock signal is used to generate the pulse signal, then the security is improved, but the pulse width varies due to PVT variations
Solution Approach 1:
The patent implements feedback mechanisms where the delay elements continuously monitor and compensate for PVT variations. The compensation circuits detect changes in delay characteristics caused by process, voltage, or temperature variations and adjust the delay accordingly to maintain constant pulse width, thereby ensuring both security and reliability
Solution Approach 2:
The patent dynamically adjusts delay parameters through compensation circuits that respond to PVT variations. By changing the effective delay value in real-time based on detected variations, the system maintains constant pulse width without requiring external clock signals, thus achieving both security and pulse width constancy
3Device complexity
If conventional delay circuits are used, then the circuit complexity is reduced, but the pulse width varies with PVT variations
Solution Approach 1:
The patent segments the delay function into multiple delay elements arranged in series, each contributing to the total delay. This segmentation allows individual elements to be compensated for PVT variations while maintaining the overall delay function, achieving pulse width constancy with moderate circuit complexity
Solution Approach 2:
The patent transforms the static delay circuit into a dynamic system that automatically adjusts its delay characteristics in response to PVT variations. The compensation circuits enable the delay elements to adapt their behavior dynamically, maintaining constant pulse width without requiring complex external control mechanisms
Data Source
AI summary
A fixed-width pulse generator includes a metastability detector circuit, a delay signal generator, and a combinational logic circuit. The metastability detector circuit is configured to receive a trigger signal and generate state detection signals. The delay signal generator is configured to receive the state detection signals and the trigger signal, and delay the trigger signal by two different delay values to generate two different delayed signals. One of the delay values is based on the state detection signals. The combinational logic circuit is configured to receive the two delayed signals and an error signal, and generate a fixed-width pulse that remains constant over process, voltage, and temperature variations.