Flag Memory Cell Arrays for Capacitive Coupling Compensation
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Solution Overview
Problem
Flash memory devices face challenges in reducing threshold voltage windows during sense operations due to capacitive coupling from neighboring memory cells, which necessitates an extra threshold voltage margin, limiting the number of read thresholds within a limited voltage window.
Innovation Solution
Incorporating additional flag memory cell arrays that provide flag data indicating whether adjacent pages have been programmed, allowing for dynamic adjustment of read gate voltages to compensate for capacitive interference, thereby optimizing threshold voltage margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an extra threshold voltage margin is added to compensate for capacitive coupling from neighboring cells, then the reliability of sense operations is improved, but the number of readable states within a limited threshold voltage window is reduced
Solution Approach 1:
The patent applies preliminary action by reading flag cells before the main sense operation to determine the programming status of adjacent pages. This advance information allows the controller to pre-adjust threshold voltage margins, ensuring accurate sense operations while maximizing the number of readable states within the voltage window.
Solution Approach 2:
The patent implements feedback by using the flag cell data to dynamically adjust the threshold voltage margins during sense operations. The flag cells provide feedback about the programming status of adjacent pages, enabling the controller to optimize read thresholds based on actual capacitive coupling conditions, thereby maintaining both reliability and adaptability.
2Measurement precision
If additional flag memory cell arrays are incorporated to track programming status, then the precision of read operations is improved, but the device complexity is increased
Solution Approach 1:
The patent merges the flag cell functionality with the existing memory cell array structure. The flag cells are integrated into the same physical array as the data storage cells, sharing the same word lines and bit lines. This merging approach enables precise tracking of programming status while minimizing the increase in device complexity by utilizing existing structural resources.
Solution Approach 2:
The flag cells serve multiple functions: they indicate the programming status of adjacent pages, enable dynamic threshold voltage adjustment, and facilitate precise read operations. This multi-functionality reduces the need for separate dedicated circuits, thereby improving read operation precision while limiting the increase in overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more precise read operations by adjusting read voltages based on adjacent page programming status, enhancing the number of readable states within a given threshold voltage window and improving memory device performance.
Implementation Method 1
As a result of capacitive coupling from neighboring memory cells, the threshold voltages of the memory cells in an even page (e.g., even bit line) depend on whether the memory cells of the neighboring odd page (e.g., odd bit line) have been programmed.
Data Source
AI summary
Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative of the memory cells coupled to the second data lines in the first array of memory cells being programmed.