Flag Retaining Circuit for Stable RFID Timer Accuracy
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Solution Overview
Problem
Passive-type RFID tags face challenges in maintaining a constant flag retention period regardless of power supply presence, leading to low timer accuracy due to varying discharge currents.
Innovation Solution
A flag retaining circuit with a first capacitor element, a flag setting unit, a flag checking unit, and a discharging unit, including a transconductance element and a control switch, which maintains a constant flag retention period by controlling discharge currents based on power supply presence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the control switch is used to control discharge current based on power supply presence, then the discharge current can be adjusted for different power conditions, but the flag retention period becomes unstable and varies depending on power supply presence
Solution Approach 1:
The patent implements a feedback mechanism where the flag checking unit continuously monitors the flag state and provides feedback to the control switch. This feedback loop allows the system to automatically adjust the discharge current based on the actual flag retention status, ensuring the retention period remains stable regardless of power supply conditions. The control switch receives control signals from the flag checking unit that reflect the current flag state, enabling dynamic compensation for power supply variations.
2Reliability
If the capacitance is discharged with a constant current when power supply is present, then the discharge process is stable, but the retention period becomes inconsistent when power supply is absent due to parasitic diode leak current
Solution Approach 1:
The patent introduces the control switch as an intermediary element between the power supply condition and the discharge process. This intermediary component mediates the discharge current based on the power supply status, preventing the direct negative impact of parasitic diode leak current when power is absent. The control switch acts as a buffer that can adjust or block the discharge path, ensuring consistent retention timing regardless of whether power is present or absent.
3Adaptability or versatility
If the same retention period is defined for both power supply present and absent conditions, then the timer can serve as a universal timing mechanism, but the accuracy of the timer decreases due to varying discharge characteristics
Solution Approach 1:
The patent applies dynamic adjustment principles where the discharge current is not fixed but varies dynamically based on power supply conditions. When power is present, the system uses one discharge characteristic, and when power is absent, it automatically transitions to a different discharge characteristic through the control switch. This dynamic adaptation allows the timer to maintain high accuracy across different operating conditions while preserving its universal timing function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures a constant flag retention period regardless of power supply presence, enhancing timer accuracy and reliability in RFID systems.
Implementation Method 1
a transconductance element having a first output end grounded and a second output end connected to said first line, for converting a voltage supplied to a control input end thereof into a current flowing between said first output end and said second output end so as to discharge said first capacitor element via said first line
Implementation Method 2
a first capacitor element; a flag setting unit connected to a power source that supplies a power-supply voltage based on the power supply, for receiving supply of an input signal and charging said first capacitor element according to said input signal
Implementation Method 3
a control switch having a first end thereof connected to a node at a direct-current voltage, a second end thereof connected to the control input end of said transconductance element, and a control end thereof connected to a second line connecting said flag checking unit and said discharging unit, for connecting or disconnecting said first end with said second end depending on the voltage on said second line
Data Source
AI summary
A flag retaining circuit comprises a first capacitor element having one end connected to a first line and the other end grounded; a flag setting unit that charges the first capacitor element according to an input signal; a flag checking unit that outputs 0 or 1 based on the potential of the first capacitor element; and a discharging unit that discharges the first capacitor element. The discharging unit includes a transconductance element that discharges the first capacitor element via the first line; a control switch that receives supply of the voltage on a second line; and a second capacitor element having one end connected to a node between a control input end of the transconductance element and the control switch, and the other end grounded. The flag checking unit outputs the inverse of the voltage on the first line onto the second line.