Flair Gate Structure for Memory Cell Programming Speed

Solution Overview

Problem

Conventional Shallow Trench Isolation (STI) technology in semiconductor memory cells results in slower programming speeds due to current variations at the bitline-STI edge, limiting optimal programming speed.

Innovation Solution

A 'flair' gate structure is formed with a wider wordline width at the bitline-STI edges compared to the center, directing the majority of the current through the central portion of the bitline, thereby reducing bitline-STI edge current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If Shallow Trench Isolation (STI) is used instead of Local Oxidation of Silicon (LOCOS), then scalability is improved, but programming speed deteriorates due to edge current effects

Engineering Contradiction:

ImprovescalabilityVSAvoidprogramming speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The gate structure implements local quality by having different widths at different locations: a first width over the center of the active region and a second width over the bitline-STI edge. This non-uniform gate width compensates for the localized edge current effects at the bitline-STI interface, allowing the structure to maintain both scalability and improved programming speed by addressing the specific problem location rather than requiring uniform structural changes throughout.

Inventive Principle:

Principle #3Local quality

2Ease of manufacture

If uniform gate structure is used, then manufacturing simplicity is maintained, but programming speed is limited due to edge current component

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidprogramming speed

Core Design Contradiction:

Ease of manufactureVSSpeed

Solution Approach 1:

The gate structure implements local quality by having different widths at different locations: a first width over the center of the active region and a second width over the bitline-STI edge. This non-uniform gate width compensates for the localized edge current effects at the bitline-STI interface, allowing the structure to maintain both scalability and improved programming speed by addressing the specific problem location rather than requiring uniform structural changes throughout.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS8367537B2Flash memory cell with a flair gate

Publication Date: 2013.02.05 MONTEREY RESEARCH LLC

AI summary

An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an active region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width.