Flank-Integrated OxRAM Memory Cell for Compact Arrays
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Solution Overview
Problem
Current OxRAM memory cells are bulkier than desired due to their structure, which hinders the miniaturization of memory cell arrays, particularly when using existing CMOS technologies.
Innovation Solution
The memory cell design integrates an OxRAM memory element with a selection transistor, where the memory element is positioned on the flank of the transistor, sharing the same material stacks, and utilizing a metal oxide layer like HfO2 or Ta2O5 with an oxidizable metal layer such as titanium or hafnium, and a conductive zone made of titanium nitride, optimized using SOI technology to minimize area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional OxRAM memory element structure is used, then the memory element can be integrated with CMOS technologies, but the overall size of the memory cell becomes bulky
Solution Approach 1:
The patent merges the memory element structure with the selection transistor structure by positioning the memory element on the flank of the transistor and sharing common material stacks (such as the high-k dielectric layer and conductive layers), thereby reducing the total area occupied by the memory cell while maintaining manufacturability with existing CMOS technologies
Solution Approach 2:
The patent transitions from a planar layout to a three-dimensional configuration by positioning the memory element vertically on the flank of the selection transistor, utilizing the vertical dimension to reduce the footprint area of the memory cell
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the overall size of the memory cell pair by minimizing the area occupied, achieving a significant reduction in dimensions from 252 nm to 172 nm, enabling more compact memory cell arrays with improved integration capabilities.
Implementation Method 1
A first application of a relatively high voltage between the conductive layers surrounding the structure leads to a localized change in the layer 4 of material exhibiting high permittivity. It is assumed that, during the application of the voltage, oxygen present in the high-k layer 4 migrates towards the titanium layer.
Implementation Method 2
one thereof is for example made of an oxidizable metal such as Ti or Hf
Implementation Method 3
By subsequently applying voltages, for example in the opposite direction to the terminals of the structure, the memory element is returned to a high resistivity state
Data Source
AI summary
The disclosure relates to a memory cell comprising a resistive RAM memory element and a selection transistor, in which the memory element is positioned on a flank of the selection transistor.