Flash-Based Accelerator Direct Memory Mapping
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Solution Overview
Problem
Existing accelerators face inefficiencies due to disconnection from non-volatile memory, leading to redundant memory allocations, data copies, and high latency in data movement between kernel-space and user-space, limiting performance improvements.
Innovation Solution
A flash-based accelerator is integrated with a host system, featuring a flash backbone, processors, memory system, and supervisor processor to directly manage and transfer data between memory and flash memory without OS assistance, reducing data copies and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If accelerators use non-volatile memory (SSD) connected to host machine to process large sets of data, then data processing capacity is improved, but data movement latency increases due to complete disconnection between accelerator and non-volatile memory
Solution Approach 1:
The patent merges the accelerator and non-volatile memory into a single integrated device, eliminating the complete disconnection between them. The accelerator processors can directly access flash memory through the integrated architecture, removing the need for data to traverse through the host machine and reducing movement latency while maintaining large data processing capacity.
Solution Approach 2:
The patent introduces a supervisor processor as an intermediary between the accelerator processors and flash memory. This supervisor processor manages memory allocation, handles address translation, and coordinates data movement, enabling efficient direct access to non-volatile memory without requiring host OS assistance or kernel-mode user-mode switching.
2Reliability
If kernel module cannot directly access user-space memory, then memory management security is improved, but memory management overhead increases due to unavoidable data copies between kernel-space and user-space
Solution Approach 1:
The supervisor processor provides self-service memory management capabilities within the integrated device, allowing accelerator processors to directly access flash memory without requiring host kernel mediation. This eliminates the mandatory data copies between kernel-space and user-space while maintaining secure memory management through the supervisor processor's control over memory allocation and access.
3Reliability
If redundant memory allocations and data copies are performed between user-space and kernel-space, then memory access control is improved, but processing speed decreases due to high overhead
Solution Approach 1:
The patent extracts memory management functions from the host operating system kernel and relocates them to the supervisor processor within the integrated device. This extraction eliminates the redundant memory allocations and data copies between user-space and kernel-space that occur in traditional architectures, while the supervisor processor maintains secure memory access control through its own memory management mechanisms.
Data Source
AI summary
A flash-based accelerator configured to be connected to a host including a CPU and a system memory is provided. A plurality of processors execute a plurality of kernels offloaded from the host. A memory system includes a first memory that is used to map a data section of each kernel to the flash memory. A supervisor processor maps a region of the first memory pointed by a data section of a first kernel to a region of the flash memory to allow first data to move between the region of the first memory and the region of the flash memory, based on a first message which is transferred in accordance with execution of the first kernel by a first processor among the plurality of processors. A network integrates the flash backbone, the memory system, the plurality of processors, and the supervisor processor.