Flash Access Circuit With Adaptive Error Correction for Wear

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Solution Overview

Problem

The increasing number of bits stored in flash memory cells, while enhancing bit density, leads to a marked decline in the lifecycle of flash memory devices, limiting their use in systems with significant write operations.

Innovation Solution

Implementing a flash access circuit that performs error code encoding and decoding using algorithms like Reed Solomon, which writes error codes to the flash memory device based on its health status, thereby extending the lifecycle by adaptively managing data and error correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of distinct voltage levels in flash memory cells is increased to store more bits, then the memory density is improved, but the lifecycle of the flash memory device deteriorates

Engineering Contradiction:
Improvememory densityVSAvoidlifecycle
Core Design Contradiction:
Quantity of substanceVSDuration of action of stationary object

Solution Approach 1:

The patent applies preliminary action by performing error correction encoding before data is written to flash memory. The system proactively generates error correction codes and writes them to designated locations in the flash memory device before actual data storage operations begin. This preliminary preparation enables the system to detect and correct errors that will inevitably occur during the flash memory's lifecycle, thereby extending the usable life of high-density memory cells without sacrificing the increased storage capacity achieved through multiple voltage levels.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the number of writes to flash memory is increased, then the productivity is improved, but the reliability of the flash memory deteriorates

Engineering Contradiction:
Improvenumber of writesVSAvoiddata reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements feedback mechanisms by continuously monitoring the health status of flash memory blocks and adaptively adjusting error correction strategies. The system reads back written data, verifies integrity using error correction codes, and uses this feedback information to make decisions about block wear leveling, error correction intensity, and when to migrate data to fresh blocks. This closed-loop feedback enables the system to maintain high write productivity while dynamically preserving data reliability even as flash memory cells degrade from repeated write operations.

Inventive Principle:
Principle #23Feedback

3Reliability

If error correction codes are written to every location in flash memory, then the reliability is improved, but the device complexity and storage overhead increase

Engineering Contradiction:
Improvedata reliabilityVSAvoidstorage overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by implementing error correction codes selectively rather than uniformly across all flash memory locations. The system identifies specific regions or blocks that require error correction based on their wear status, error history, and importance, then applies error correction encoding only to those locations. This localized approach maintains data reliability for critical stored information while reducing the overall storage overhead and complexity compared to applying error correction universally to every byte in the flash memory device.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20110060968A1Systems and Methods for Implementing Error Correction in Relation to a Flash Memory
Publication Date: 2011.03.10 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US20110060968A1 patent drawing
  • US20110060968A1 patent drawing
  • US20110060968A1 patent drawing

AI summary

Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a flash memory device and a flash access circuit. The flash access circuit is operable to perform an error code encoding algorithm on a data set to yield an error code, to write the data set to the flash memory device at a first location, and to write the error code to the flash memory device at a second location.