Flash Memory Access Scheduling for Real-Time Response

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Solution Overview

Problem

Flash memory systems face challenges in providing real-time responsiveness and high data reliability due to the need for erase-before-write operations, limited erase cycles, and the overhead of garbage collection and wear leveling, which can delay response times to host requests.

Innovation Solution

A flash memory system with a controller that employs a control program to manage access operations by suspending and resuming tasks based on assigned times, utilizing multithreading and a flash translation layer to optimize write operations, garbage collection, and wear leveling, ensuring real-time responsiveness and high data reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If background operations (garbage collection, wear leveling) are performed concurrently with access requests, then data reliability and memory management are improved, but response time to host requests deteriorates

Engineering Contradiction:

Improvedata reliabilityVSAvoidresponse time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements dynamic operation scheduling where the controller adaptively switches between executing background operations and handling access requests based on operation status and timing. The control program dynamically adjusts execution priorities, suspending background operations when access requests arrive and resuming them during idle periods, thereby optimizing both data reliability and response time

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent performs preliminary actions by executing background operations during idle times before new access requests arrive. The controller proactively completes garbage collection and wear leveling tasks during periods when no host requests are pending, ensuring memory health is maintained without impacting future response times

Inventive Principle:

Principle #10Preliminary action

2Device complexity

If access operations are executed sequentially, then resource management is simplified, but productivity and real-time responsiveness deteriorate

Engineering Contradiction:

Improvecontrol complexityVSAvoidaccess speed

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent segments access operations into multiple threads that can execute concurrently. The control program divides the execution flow into separate threads for background operations and access requests, allowing parallel execution while maintaining individual thread management simplicity. This segmentation enables multithreaded processing without significantly increasing overall control complexity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent ensures continuous productive action by eliminating idle wait times in the control program. Through multithreading, the controller continuously processes access requests and background operations without sequential delays, maintaining constant productive activity and improving real-time responsiveness while managing complexity through structured thread execution

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS20110302476A1Memory system and method of accessing a semiconductor memory device

Publication Date: 2011.12.08 SAMSUNG ELECTRONICS CO LTD

AI summary

A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.