Folded-Reference Flash ADC for Lower Capacitance Conversion
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs), particularly flash ADCs, face challenges in reducing capacitance while maintaining high-speed conversion and resolution, which is essential for broadband digital communication and optical storage applications.
Innovation Solution
A flash ADC design that includes a first unit to determine the most significant bit (MSB) of an analog input signal and a second unit with comparators to determine remaining bits, where the reference voltage is varied based on the MSB determination result, allowing for shared use of comparators and reduced input capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of comparators is reduced to lower capacitance, then the conversion speed and resolution may be compromised, but the patent achieves high-speed conversion with reduced capacitance through dynamic reference voltage control
Solution Approach 1:
The patent applies dynamics by dynamically adjusting the reference voltage based on the MSB value. The reference voltage control unit changes the reference voltage from a fixed value to a variable value that depends on the MSB determination result. This dynamic adjustment allows the system to maintain high conversion speed while using fewer comparators, thereby reducing capacitance without sacrificing productivity.
Solution Approach 2:
The patent changes the parameter of reference voltage from constant to variable. By modifying the reference voltage parameter based on the MSB state (applying different voltages for MSB=0 and MSB=1), the system optimizes the performance of remaining comparators. This parameter change enables the reduced set of comparators to achieve the same conversion speed and resolution that would otherwise require more comparators and higher capacitance.
2Productivity
If a traditional flash ADC structure is used to maintain high conversion speed, then the device size and power consumption increase, but the patent reduces device complexity while maintaining performance
Solution Approach 1:
The patent extracts and separates the MSB determination function from the main comparison process. By having a dedicated first ADC unit handle MSB determination and using its result to control the reference voltage for the second ADC unit, the patent eliminates the need for a full set of comparators required in traditional flash ADCs. This extraction reduces device complexity and size while maintaining high conversion speed through the optimized comparison process.
Solution Approach 2:
The reference voltage control unit serves multiple functions: it monitors the MSB determination result, selects appropriate reference voltage levels, and adjusts the reference voltage in real-time. This multi-functional component replaces what would traditionally require multiple dedicated circuits, thereby reducing overall device complexity while maintaining the high-speed conversion capability through intelligent voltage management.
Data Source
AI summary
A folded reference voltage flash analog-to-digital (ADC) converter and a method thereof are provided. The flash ADC of the present invention determines the most significant bit (MSB) of an analog input signal, varies a reference voltage input to a plurality of comparators in accordance with the MSB determination result, and determines the remaining bits. Accordingly, input capacitance can be reduced while maintaining the size and power consumption of the ADC.