Fast Flash ADC Window Detection for Fly Capacitor Balancing
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Solution Overview
Problem
Conventional control methods for multi-level power converters struggle with efficiently balancing the voltages across fly capacitors due to dynamic system variables, particularly the voltage across each capacitor, which is a crucial factor for maintaining charge balance.
Innovation Solution
A 2-bit fast flash analog-to-digital converter (ADC) circuit is designed to quickly and efficiently balance fly capacitor voltages in multi-level converters by using a 2-bit fast flash ADC circuit with only three comparators, providing high conversion speed, high resolution, small layout area, and low power consumption, while dynamically adjusting the voltage window based on capacitor status.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional control methods with long sequences of power switch states are used, then charge balance can be achieved under constant system variables, but the method becomes unrealistic and inefficient when system variables are dynamic
Solution Approach 1:
The patent implements dynamic voltage detection by continuously monitoring fly capacitor voltages during operation and using this real-time information to control power switch states. This replaces static, pre-determined control sequences with adaptive control that responds to changing system conditions, resolving the contradiction between maintaining charge balance reliability and reducing control complexity under dynamic operating conditions
Solution Approach 2:
The patent employs feedback mechanisms where the detected voltage across each fly capacitor is fed back to the control circuit, which then adjusts the power switch states accordingly. This closed-loop control ensures charge balance is maintained dynamically without requiring complex open-loop sequences, addressing both the reliability and complexity concerns
2Adaptability or versatility
If multi-level converter circuit complexity increases, then more voltage levels can be generated, but determining suitable charge-balance methods becomes exceedingly difficult
Solution Approach 1:
The patent segments the charge-balance control problem by independently detecting and controlling each fly capacitor's voltage. Instead of attempting to manage the entire multi-level system as a single complex entity, the invention divides the problem into manageable units (individual capacitors), each with its own voltage detection and control strategy, thereby reducing the overall difficulty of charge-balance determination
Solution Approach 2:
The patent introduces voltage detection circuits as intermediary elements between the fly capacitors and the control system. These intermediaries simplify the interface by providing direct voltage measurements to the controller, making it easier to determine appropriate charge-balance methods without directly confronting the full complexity of the multi-level converter architecture
3Measurement precision
If high conversion speed and high resolution are achieved in ADC, then fly capacitor voltage balancing is improved, but power consumption and layout area increase
Solution Approach 1:
The patent implements a 2-bit flash ADC that provides partial voltage measurement information (coarse resolution) rather than attempting full high-resolution conversion. This partial action approach achieves sufficient voltage balancing capability without the excessive power consumption and area requirements of full high-resolution ADCs, resolving the contradiction between measurement precision and power/area efficiency
Data Source
AI summary
A 2-bit fast flash analog-to-digital converter circuit and related methods designed for use with multi-level converters in particular to achieve: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements for properly balancing fly capacitor voltages. One embodiment includes a voltage input configured to be coupled to a multi-level converter fly capacitor; a comparator coupled to the voltage input and a first reference voltage input and having a first binary output indicating whether the input voltage is higher or lower than a voltage on the first reference voltage input; and a circuit coupled to the voltage input and to second and third reference voltage inputs, the circuit configured to provide a second binary output indicating whether the input voltage is inside or outside a voltage window defined by respective voltages on the second reference and third reference voltage inputs.