Flash ADC Code Shuffling for High Linearity and Fast Settling
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Solution Overview
Problem
Conventional analog-to-digital converters face challenges in achieving high-linearity due to device mismatches and variations, leading to spurs and tones in the output signal, which are not effectively mitigated by existing technologies.
Innovation Solution
A flash analog-to-digital converter system that employs code-shuffling circuitry to periodically shuffle digital codes among multiple resistive digital-to-analog converters (RDACs), generating reference voltages that reduce the effects of mismatches, and incorporates active or passive subtractor circuits and latch circuits to generate and latch difference signals, thereby minimizing spurs and tones without the need for physical multiplexing of analog reference voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical multiplexing of analog reference voltages is used to reduce mismatches, then linearity improves, but settling time increases and latency is added
Solution Approach 1:
The patent uses digital copies of reference codes instead of physical analog multiplexing. Multiple RDACs hold copies of reference codes in digital form, and code-shuffling circuitry permutes these digital copies to generate shuffled reference codes. This eliminates the need for physical multiplexing of analog voltages, thereby reducing settling time and latency while maintaining linearity through digital manipulation of reference values.
Solution Approach 2:
The patent replaces the mechanical/physical analog multiplexing system with a digital code-shuffling system. Instead of physically switching analog reference voltages through multiplexers (which introduces settling time and latency), the system uses digital code-shuffling circuitry to permute digital reference codes that are then converted to analog by multiple parallel RDACs. This substitution of digital for physical analog manipulation resolves the time-performance contradiction.
2Object-generated harmful factors
If device mismatches are reduced through conventional methods, then spurs and tones are mitigated, but linearity is still compromised
Solution Approach 1:
The patent implements periodic code-shuffling where reference codes are systematically permuted across multiple RDACs in a repeating pattern. This periodic shuffling ensures that mismatches in individual RDACs are averaged out over time, reducing spurs and tones while maintaining high linearity. The periodic nature of the shuffling pattern allows for predictable cancellation of mismatch effects without compromising the overall conversion accuracy.
Solution Approach 2:
The patent changes the parameter of reference code assignment by dynamically shuffling which digital reference code is assigned to which RDAC. Instead of fixed assignments that expose mismatches, the system periodically changes the mapping between reference codes and RDACs. This parameter change in code assignment patterns allows mismatch effects to be distributed and averaged, reducing spurs and tones while preserving linearity through the statistical averaging of mismatch errors.
3Measurement precision
If code-shuffling is implemented to reduce mismatches, then linearity improves, but additional circuit complexity is introduced
Solution Approach 1:
The patent merges the code-shuffling function with the existing reference generation architecture by integrating code-shuffling circuitry into the digital domain before the RDACs. Instead of adding separate complex analog multiplexing and switching networks, the shuffling is performed on digital codes that then feed into standard RDAC blocks. This merging of shuffling functionality with the digital reference generation path achieves linearity improvement while minimizing additional circuit complexity by reusing existing RDAC hardware.
Data Source
AI summary
An analog-to-digital converter circuit comprises code-shuffling circuitry, a plurality of digital-to-analog converter circuits, a plurality of difference circuits, and a plurality of latch circuits. The code-shuffling circuitry is operable to shuffle a plurality of digital codes among a plurality of its outputs. The plurality of digital-to-analog converter circuits are operable to convert a digital code on the respective one of the outputs to a corresponding one of a plurality of analog reference voltages. The plurality of difference circuits is operable to generate a respective one of a plurality of difference signals corresponding to a difference between an input voltage and a respective one of the plurality of reference voltages. The plurality of latch circuits is operable to latch a respective one of the plurality of difference signals to a corresponding one of a plurality of digital values.