Flash ADC Comparator Calibration for Quantization Noise Reduction
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Solution Overview
Problem
Flash ADCs in ΔΣ converters face significant quantization noise due to comparator offsets, which can be near the level of thermal noise, causing many ΔΣ ADCs to fail in meeting noise specifications, especially since these offsets are process-dependent and affect the resolution of the ADC.
Innovation Solution
A calibration system is implemented that includes a reference shuffling circuit, a calibration circuit, and digital logic to adjust comparator offsets, using techniques like data weighted average, leap-frogging, and swapping schemes, along with algorithms like random walk, simulated annealing, and genetic algorithms to minimize quantization noise by ensuring all comparators experience transitions over time, even with small input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If comparator offset correction is not applied, then the ADC structure remains simple and manufacturing is easier, but quantization noise becomes significant and noise specifications are not met
Solution Approach 1:
The patent applies preliminary action by performing offset calibration of comparators before the ADC enters normal operation. The calibration circuit measures and stores offset values for each comparator in advance, so that when the ADC operates, the quantization noise is already minimized without requiring real-time calibration intervention.
Solution Approach 2:
The patent introduces an intermediary calibration circuit that acts as a mediator between the comparators and the main ADC processing path. This calibration circuit includes offset measurement logic and storage elements that intermediate the offset correction process, allowing the main ADC to operate without direct calibration intervention while still benefiting from reduced quantization noise.
2Measurement precision
If all comparators are calibrated using static DC method, then offset correction is achieved, but the calibration process is time-consuming and requires taking ADC blocks offline
Solution Approach 1:
The patent applies periodic action by implementing calibration sequences that systematically activate and measure each comparator in turn rather than attempting simultaneous calibration of all comparators. The calibration logic controls comparators periodically through structured sequences, which reduces calibration time while maintaining measurement precision through systematic coverage of all comparators.
3Object-affected harmful factors
If oversampling ratio is increased to reduce thermal noise, then thermal noise is reduced, but quantization noise from flash comparators remains significant and dominates the noise budget
Solution Approach 1:
The patent converts the harmful effect of comparator offsets into a benefit by measuring and compensating for these offsets through calibration. The calibration process transforms the previously harmful quantization noise caused by offsets into a controllable parameter that can be corrected, thereby reducing overall noise and improving ADC performance.
Data Source
AI summary
A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.