Double Data Rate Flash ADC Comparator for Reduced Kickback Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash ADCs in mobile communication devices face challenges with kickback noise affecting accuracy and power consumption, as existing solutions like preamplifiers increase complexity and reduce battery life.
Innovation Solution
The proposed solution involves a double data rate comparator core that operates on both edges of a clock cycle, using floating voltage references and a clock inverter circuit to reduce kickback noise, and eliminates the need for preamplifiers by employing a switched capacitor network, thereby reducing power consumption and increasing conversion accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If preamplifiers are inserted before each comparator to prevent kickback noise, then measurement precision is improved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent extracts and removes the preamplifier stage from the comparator structure, replacing it with a modified comparator design that achieves kickback noise rejection without the additional amplification stage, thereby reducing power consumption while maintaining conversion accuracy
Solution Approach 2:
The patent converts the harmful kickback noise effect into a beneficial signal by using the noise transient to rapidly charge capacitors to reference voltages, thereby eliminating the need for preamplifiers and reducing power consumption while maintaining or improving measurement precision
2Measurement precision
If preamplifiers are inserted before each comparator to prevent kickback noise, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts and removes the preamplifier stage from the comparator structure, replacing it with a modified comparator design that achieves kickback noise rejection without the additional amplification stage, thereby reducing device complexity while maintaining conversion accuracy
Solution Approach 2:
The patent merges the kickback noise transient effect into the reference voltage generation process, combining what was previously a harmful interference with the useful function of setting comparator reference levels, thereby eliminating the need for separate preamplifier circuits and reducing overall ADC complexity
3Use of energy by moving object
If floating voltage sources are used to reduce power consumption, then power consumption is reduced, but kickback transients distort the input signal
Solution Approach 1:
The patent converts the harmful kickback transients into a beneficial effect by using them to rapidly charge capacitors to the correct reference voltages, thereby maintaining power efficiency while eliminating signal distortion through clever circuit timing and capacitor coupling
Solution Approach 2:
The patent performs preliminary action by using the kickback transient to pre-charge the capacitors to the appropriate reference voltage levels before the actual comparison operation, ensuring that the input signal is not distorted while maintaining the power benefits of floating voltage sources
Data Source
AI summary
A flash analog to digital converter (ADC) includes a first, second, and third double data rate comparator core configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the comparator core. An inverted comparator clock coupled to the third comparator core reduces kickback noise. The ADC includes a first and a second floating voltage reference configured to shift a voltage of a differential comparator input by a fixed amount, and produce the first and second differential input signal. The third comparator core is cross coupled between the first and second comparator core.