Flash ADC Calibration and Rectification for Low-BER DSP Receivers

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Solution Overview

Problem

DSP-based serial receivers face challenges in achieving low bit error rate (BER) at high speeds while maintaining low power and area requirements, as traditional ADCs require excessive power and area due to the need for numerous comparators.

Innovation Solution

The integration of calibration and error detection/correction features, such as distributed offset calibration and redundant comparators, along with low BER rectification, reduces the number of comparators needed in a flash ADC, allowing for high-speed operation with reduced power and area consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a traditional N-bit flash ADC is used to achieve low BER, then the bit error rate performance is improved, but the power consumption and area increase exponentially with resolution

Engineering Contradiction:

Improvebit error rateVSAvoidADC area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The ADC conversion process is divided into two separate stages: a first flash ADC performs a coarse conversion to determine the most significant bit and an intermediate value, then a second flash ADC performs a fine conversion on the remaining signal. This segmentation allows each converter to operate at lower resolution, reducing the number of comparators needed in each stage while maintaining overall high conversion accuracy and low BER performance

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first flash ADC performs a preliminary coarse conversion before the second flash ADC performs the fine conversion. By removing the most significant bit and intermediate value in advance, the second converter only needs to resolve the remaining less significant bits, reducing its comparator requirements while maintaining overall conversion accuracy

Inventive Principle:

Principle #10Preliminary action

2Reliability

If a traditional N-bit flash ADC is used to achieve low BER, then the bit error rate performance is improved, but the power consumption increases exponentially with resolution

Engineering Contradiction:

Improvebit error rateVSAvoidADC power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Inventive Principle:

Principle #10Preliminary action

3Area of stationary object

If pipeline or SAR ADCs are used to reduce comparators, then area and power are reduced, but the clock rate decreases and low BER at high speed cannot be achieved

Engineering Contradiction:

ImproveADC areaVSAvoidclock rate

Core Design Contradiction:

Area of stationary objectVSSpeed

Solution Approach 1:

The conversion process is segmented into two independent flash ADC stages operating in sequence. Each stage uses a comparator array appropriate for its resolution requirement, allowing the system to achieve high-speed flash ADC performance for the coarse conversion while using a smaller comparator array for the fine conversion, thereby maintaining high overall conversion speed with reduced area

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first flash ADC performs a preliminary coarse conversion at high speed before the second flash ADC performs the fine conversion. This preliminary action at high clock rate enables the overall system to achieve multi-GHz operation while maintaining low BER performance through the combination of both conversion stages

Inventive Principle:

Principle #10Preliminary action

4Reliability

If more interleaved alternative ADCs are used to achieve low BER at high speed, then the BER performance is improved, but the power and area increase

Engineering Contradiction:

Improvebit error rateVSAvoidtotal power consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8836553B2DSP reciever with high speed low BER ADC

Publication Date: 2014.09.16 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.