Flash ADC Calibration for Comparator Offset and Reference Mismatch
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Solution Overview
Problem
Flash analog to digital converters with systematic offsets in comparator circuits fail to operate properly, leading to operation failures due to mismatched common mode levels and reference voltages.
Innovation Solution
Incorporating double differential comparator circuits and a calibration circuit that outputs test signals to calibrate the common mode levels and reference voltages based on the distribution of generated signals, adjusting resistors to correct systematic offsets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all comparator circuits use the same circuit architecture, then device complexity is reduced, but systematic offset causes operation failure
Solution Approach 1:
The patent introduces different circuit architectures for different comparator circuits based on their specific offset characteristics. First comparator circuits use one architecture while second comparator circuits use another, allowing each circuit to be optimized for its local conditions and eliminating systematic offsets without requiring complex calibration procedures.
2Reliability
If calibration is performed to eliminate systematic offset, then operation reliability is improved, but calibration complexity increases
Solution Approach 1:
The patent performs calibration actions during the manufacturing process rather than requiring separate field calibration procedures. Test signals are applied and comparator outputs are observed during fabrication, allowing offset compensation to be built into the circuit before deployment, thus improving reliability without adding complex calibration infrastructure.
3Measurement precision
If test signals are applied to observe comparator output, then measurement precision is improved, but measurement time increases
Solution Approach 1:
The patent applies test signals periodically during the manufacturing process to observe comparator outputs and determine appropriate circuit architectures. This periodic measurement approach allows precise offset detection to be integrated into existing manufacturing workflows without requiring additional dedicated calibration time beyond normal production cycles.
Data Source
AI summary
A flash analog to digital converter includes double differential comparator circuits and a calibration circuit. Each double differential comparator circuit compares a first input signal with a corresponding voltage in a first set of reference voltages, and compares a second input signal with a corresponding voltage in a second set of reference voltages, in order to generate a corresponding signal in first signals. The calibration circuit outputs a first test signal to be the first input signal and outputs a second test signal to be the second input signal in a test mode, and calibrates a common mode level of each of the first input signal and the second input signal, or calibrates at least one first reference voltage in the first set of reference voltages and at least one second reference voltage in the second set of reference voltages according to a distribution of the first signals.