Flash ADC Reference Shuffling for High-Speed Mismatch Correction
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Solution Overview
Problem
Flash ADCs face challenges in high-speed operations due to delays introduced by digital logic in dynamic element matching schemes and complex switching techniques required to address DAC unit element mismatches, which are not suitable for high-speed applications.
Innovation Solution
A flash ADC circuit with a switching network that swaps the orientation of reference voltages between comparators, allowing for simultaneous comparison at different reference levels without the need for complex digital shuffling, thereby simplifying the shuffling process and enabling high-speed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dynamic element matching schemes are applied to perform shuffling in the digital domain, then DAC unit element mismatch is corrected, but digital logic delay is introduced which is unacceptable for high-speed applications
Solution Approach 1:
The patent performs shuffling of comparator outputs before they are sent to the DAC, rather than after DAC conversion. By reordering the comparator outputs in advance based on the actual physical layout of the voltage ladder, the system corrects for DAC unit element mismatches before the conversion process begins, eliminating the need for post-conversion digital shuffling and its associated delays
Solution Approach 2:
The patent creates a digital representation of the physical voltage ladder arrangement and uses this information to shuffle comparator outputs accordingly. This digital model allows the system to compensate for physical mismatches without requiring complex real-time digital processing after conversion
2Loss of time
If shuffling is performed on the ADC side to address DAC mismatch, then digital logic delay is reduced, but complex switching techniques and routing circuitry are required
Solution Approach 1:
The patent applies shuffling only to specific comparator outputs that correspond to non-ideal voltage ladder elements, rather than implementing a complete switching network for all comparators. This selective approach addresses the mismatch problem locally where it exists, avoiding the need for complex global switching circuitry
Solution Approach 2:
The patent changes the ordering parameter of comparator outputs to match the physical arrangement of the voltage ladder. By reindexing or reordering the digital signals based on their physical origin rather than their logical sequence, the system achieves shuffling without complex switching mechanisms
Data Source
AI summary
A flash ADC circuit may include a reference ladder providing reference signals and a plurality of comparators, each providing an output based on a comparison of a pair of input signals to a pair of reference signals. At least one pair of the comparators may receive the same pair of reference signals with a different orientation of the reference signals at each of the comparators. The flash ADC may include a switch network for swapping the pair of reference signals between the pair of comparators.