Flash ADC Interpolation Slices for Lower Comparator Count
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Solution Overview
Problem
Existing high-speed analog-to-digital converters (ADCs) in multi-gigabit serial data links face challenges with resolution, conversion time, power consumption, and input load, particularly as the number of bits increases.
Innovation Solution
Implementing an ADC design that reduces the number of comparators by using interpolation circuits, specifically SR latches, to determine which comparator comes earlier based on input signal levels, thereby reducing conversion time, load, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of comparators is increased to improve resolution, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The ADC is divided into multiple interpolation slices, each handling a subset of the resolution. Each slice uses fewer comparators (e.g., 2 comparators per slice) to determine a portion of the output bits. The overall resolution is achieved by combining results from multiple slices rather than using one large comparator array, thus reducing total comparator count while maintaining resolution.
Solution Approach 2:
The patent transitions from a single-dimensional approach (one large comparator array) to a multi-dimensional approach by organizing comparators into multiple interpolation slices that process different portions of the signal. This dimensional reorganization allows the system to achieve the same resolution with fewer total comparators by distributing the comparison task across multiple smaller units.
2Measurement precision
If the number of comparators is increased to improve resolution, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The power consumption issue is addressed by segmenting the comparator array into multiple interpolation slices. Each slice uses minimal comparators (e.g., 2 comparators) to generate a subset of output bits. The total power consumption is significantly reduced compared to a conventional flash ADC with a full comparator array, while the resolution is maintained through the combined output of all slices.
3Measurement precision
If the number of comparators is increased to improve resolution, then measurement precision is improved, but conversion time increases
Solution Approach 1:
The conversion process is segmented into parallel operations across multiple interpolation slices. Each slice independently performs comparisons and generates output bits simultaneously. This parallel processing approach maintains fast conversion speed while achieving high resolution through the combination of results from all slices, avoiding the time penalty that would result from sequential processing.
4Measurement precision
If the number of comparators is increased to improve resolution, then measurement precision is improved, but circuit area increases
Solution Approach 1:
The circuit area is reduced by segmenting the ADC into multiple interpolation slices, each using minimal comparators. Instead of implementing one large comparator array that would occupy significant area, the patent distributes the comparison function across multiple small slices. Each slice's small footprint is multiplied by the number of slices, resulting in total area that is significantly smaller than a conventional flash ADC with equivalent resolution.
Solution Approach 2:
The patent reorganizes the circuit layout from a single large comparator array into multiple small interpolation slices arranged in a distributed configuration. This spatial reorganization reduces the peak area requirement by utilizing parallel processing units that can be efficiently packed, thereby reducing overall circuit area while maintaining the required resolution.
Data Source
AI summary
An analog-to-digital converter (ADC) circuit includes a first comparator circuit, a second comparator circuit, and an interpolation circuit. The first comparator circuit includes a first input terminal to receive a first reference voltage signal and a second input terminal to receive an input voltage signal. The second comparator circuit includes a first input terminal to receive a second reference voltage signal and a second input terminal to receive the input voltage signal. The interpolation circuit includes a first input terminal coupled to a first output terminal of the first comparator and a second input terminal coupled to a first output terminal of the second comparator.