Self-Calibrating Flash ADC With Tri-State Comparator Threshold Tuning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional high-speed analog-to-digital converters, such as flash ADCs, face challenges with high power consumption and large chip size due to increased resolution, limiting their application beyond 8-bit resolution, and require significant power dissipation and larger input capacitance.
Innovation Solution
A low power and high-speed analog-to-digital converter design utilizing tri-state inverters with adjustable aspect ratios to generate threshold voltages, coupled with diode connected inductive peaking circuits and a self-calibration mechanism via duty cycle estimation to select optimal comparators and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If flash ADC architecture is used to achieve high conversion speed, then conversion speed is improved, but power consumption and chip size increase exponentially with resolution
Solution Approach 1:
The patent divides the conventional single-stage flash ADC into multiple pipeline stages, where each stage processes a portion of the conversion. This segmentation reduces the number of comparators required in each stage, thereby reducing power consumption and chip size while maintaining high conversion speed through parallel processing across stages.
Solution Approach 2:
The patent employs dynamic element matching (DEM) techniques where comparator inputs are dynamically switched and reassigned across different conversion cycles. This dynamic reconfiguration allows the same hardware resources to serve multiple functions, reducing the overall number of comparators needed and thus lowering power consumption while maintaining conversion speed.
2Speed
If flash ADC architecture is used to achieve high conversion speed, then conversion speed is improved, but chip size increases exponentially with resolution
Solution Approach 1:
The patent divides the conventional single-stage flash ADC into multiple pipeline stages, where each stage processes a portion of the conversion. This segmentation reduces the number of comparators required in each stage, thereby reducing power consumption and chip size while maintaining high conversion speed through parallel processing across stages.
Solution Approach 2:
The patent implements a nested structure where smaller flash converter units are embedded within a pipeline architecture. Each pipeline stage contains a simplified flash converter with fewer comparators, and these stages are nested sequentially to achieve the full resolution conversion, reducing overall chip size compared to a single large flash converter.
3Measurement precision
If resolution is increased in flash ADC, then measurement precision is improved, but power consumption and chip size grow exponentially
Solution Approach 1:
The patent divides the conventional single-stage flash ADC into multiple pipeline stages, where each stage processes a portion of the conversion. This segmentation reduces the number of comparators required in each stage, thereby reducing power consumption and chip size while maintaining high conversion speed through parallel processing across stages.
Solution Approach 2:
The patent employs periodic calibration and adjustment cycles where comparator thresholds are dynamically adjusted based on input signal characteristics. This periodic optimization ensures high measurement precision across different operating conditions while maintaining lower average power consumption by activating full precision only when needed.
4Measurement precision
If resolution is increased in flash ADC, then measurement precision is improved, but chip size grows exponentially
Solution Approach 1:
The patent divides the conventional single-stage flash ADC into multiple pipeline stages, where each stage processes a portion of the conversion. This segmentation reduces the number of comparators required in each stage, thereby reducing power consumption and chip size while maintaining high conversion speed through parallel processing across stages.
Solution Approach 2:
The patent implements a nested structure where smaller flash converter units are embedded within a pipeline architecture. Each pipeline stage contains a simplified flash converter with fewer comparators, and these stages are nested sequentially to achieve the full resolution conversion, reducing overall chip size compared to a single large flash converter.
Data Source
AI summary
In a precisely self-calibrating high-speed analog to digital converter the aspect ratios of tri-state inverters are adjusted to fine-tune threshold voltage as comparators. And the multiplexers composed of tri-state inverters amplify the signal from the output of comparators. Their switches of tri-state inverters may be properly controlled to select the optimal channels and reduce unnecessary power consumption. The calibration circuitry utilizes under-sampling to calculate the duty cycles of comparators, selecting the optimal comparators and channels. By the way, the invention may avoid process variation.