Flash ADC Tree Architecture for Lower Comparator Accuracy Demands
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Solution Overview
Problem
Conventional flash ADCs face limitations in achieving high accuracy and low power consumption due to the high number of comparators required, high power consumption, and sensitivity to noise, which makes them impractical for precisions beyond 8 bits.
Innovation Solution
The proposed architecture employs a tree structure of amplifiers and offset adders to reduce the requirements on comparators, allowing for high accuracy and low power consumption, eliminating the need for a resistive or capacitive ladder, and enabling calibration for improved accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional flash ADC architecture with resistive ladder and comparators is used, then conversion speed is high, but power consumption is very high and chip area is large
Solution Approach 1:
The patent extracts and removes the resistive ladder from the conventional flash ADC architecture, replacing it with a current source and capacitor network. This elimination of the resistive ladder directly reduces power consumption while maintaining the high-speed comparison function through alternative current steering mechanisms.
Solution Approach 2:
The patent substitutes the resistive voltage division mechanism with a capacitive charge storage and current steering mechanism. Instead of using resistors to create voltage taps, the invention uses capacitors to store charge and current sources to steer signals, fundamentally changing the physical mechanism while preserving functionality.
2Speed
If conventional flash ADC architecture with resistive ladder is used, then conversion speed is high, but chip area is large
Solution Approach 1:
The patent removes the resistive ladder which occupies significant chip area, replacing it with a compact arrangement of capacitors and current sources. This extraction of the bulky resistive network directly reduces chip area while maintaining high-speed operation through the alternative capacitive approach.
Solution Approach 2:
The patent changes the fundamental operating parameters from resistive voltage division to capacitive charge storage and current steering. By changing the physical domain from resistive to capacitive, the chip area is reduced while maintaining the high-speed comparison capability essential for flash ADC operation.
3Device complexity
If conventional flash ADC architecture is used, then simple logic structure is maintained, but measurement precision is limited by comparator offset
Solution Approach 1:
The patent applies preliminary action by pre-charging capacitors to reference voltage levels before the actual conversion process. This pre-conditioning of the capacitive network establishes accurate reference levels that compensate for comparator offsets, improving measurement precision without adding complex correction logic.
Solution Approach 2:
The patent implements feedback mechanisms where the output of comparators is used to control current steering and capacitor discharge patterns. This feedback loop allows the system to correct for comparator offsets and achieve higher precision while maintaining relatively simple logic structure through iterative refinement.
4Measurement precision
If ladder impedance is reduced to minimize noise sensitivity, then measurement precision improves, but power consumption increases
Solution Approach 1:
The patent substitutes the resistive ladder with a capacitive network, fundamentally changing the mechanism for establishing reference levels. Capacitors naturally hold charge without continuous power consumption, providing noise immunity through charge stability rather than low impedance, thus achieving precision without the power penalty of high current draw.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed, low-current operation with reduced chip area, achieving 7-bit or higher accuracy while consuming less than 50 mW at 6-bit operation, and allows for additional bits of resolution without increasing amplifier levels.
Implementation Method 1
an amplifier for amplifying the input signal
Implementation Method 2
offset adders for applying two or more different offsets to the input signal
Implementation Method 3
a plurality of comparators for comparing the two or more output signals to a predefined value
Data Source
AI summary
The subject matter discloses a flash analog to digital converter arranged in a tree of signal amendment units, each comprises an amplifier and an offset adder. The output signals of the tree are even partitioned and compared to comparators, to reduce the level of accuracy required from the comparators. The subject matter also discloses a cascade of amplifiers connected in series and operate in delay one relative to the other, each amplifier comprises a reset unit to reset the amplifier responsive to receipt of a signal.