Flash Memory Assistant Gate Reduces Operating Voltage
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Solution Overview
Problem
Flash memory technologies face challenges in scaling down due to high operating voltage requirements, which complicates the fabrication of high-voltage transistors and increases costs, especially in advanced generations, as the dimension of floating gates scales down but voltage demands remain high.
Innovation Solution
A novel flash memory structure is introduced with an additional assistant gate that shares the operating voltage with the floating gates, improving the coupling ratio and reducing the required voltage for programming and erasing, allowing for further miniaturization of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the dimension of floating gate is increased to improve coupling ratio, then the required operating voltage is reduced, but the dimension of entire memory cell is increased
Solution Approach 1:
The gate structure is segmented into multiple components: a conventional floating gate and an additional assistant gate. This segmentation allows the assistant gate to provide additional coupling enhancement without requiring the main floating gate to be enlarged, thus reducing operating voltage while maintaining compact memory cell dimensions.
Solution Approach 2:
The assistant gate is positioned in a different spatial dimension - located between the two floating gates in the vertical stacking direction rather than increasing the lateral dimensions. This dimensional approach provides additional coupling area without expanding the planar footprint of the memory cell.
2Length of moving object
If process technology is advanced to scale down floating gate dimension, then device miniaturization is achieved, but the required voltages for programming and erasing are not scaled down
Solution Approach 1:
By segmenting the gate function between the floating gate and assistant gate, each component can be scaled down proportionally with process technology while the combined coupling effect maintains sufficient strength to enable lower programming and erasing voltages in advanced nodes.
Solution Approach 2:
The assistant gate acts as an intermediary element that enhances the electric field coupling between the control gate and floating gate. This intermediary structure allows for more efficient charge transfer during programming and erasing operations, reducing the voltage requirements even as dimensions are scaled down.
3Use of energy by moving object
If high-voltage transistor fabrication is improved to meet voltage requirements, then programming and erasing can be performed, but fabrication complexity and cost increase
Solution Approach 1:
The assistant gate structure changes the electrical parameters of the memory cell by providing enhanced coupling, which allows standard low-voltage transistors to achieve the same programming and erasing capability that previously required high-voltage transistors, thereby simplifying fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The assistant gate structure effectively reduces the operating voltage needed for programming and erasing, enabling smaller memory cell dimensions and simplifying the peripheral high-voltage circuit requirements, thus supporting device miniaturization and cost reduction.
Implementation Method 1
an additional assistant gate that shares the operating voltage with the floating gates
Implementation Method 2
data erasing is generally achieved by utilizing reverse Fowler-Nordheim tunneling
Implementation Method 3
The principle of programming in flash memory is to write electrons into the floating gate of memory cell by utilizing method of hot electron injection and source side injection
Implementation Method 4
The coupling ratio of floating gate decides the reading/programming speed of the flash memory. The coupling ratio of floating gate is related to the overlapping area between floating gate and source
Data Source
AI summary
A flash memory with assistant gates, including two floating gates disposed on a substrate, an insulating layer formed on the two floating gates and the substrate, an assistant gate disposed between the two floating gates, wherein a portion of the assistant gate wraps around the two floating gates, and two select gates disposed respectively outside the two floating gates and partially overlap the two floating gates.


