Flash-Backed DIMM Integrating SPD Storage and Power Backup

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Digital processing devices using volatile memory face data loss during power failures, and existing solutions require additional non-volatile memory to store parameters like Serial Presence Detect (SPD) information, leading to increased costs and component count.

Innovation Solution

A flash-backed dual in-line memory module (DIMM) with non-volatile memory, volatile memory, and a controller that uses a backup power source to temporarily store data from volatile memory to non-volatile memory during power failures, eliminating the need for a separate EEPROM and optimizing power usage by putting inactive DRAM chips into low power states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate non-volatile memory is added to store SPD information, then data integrity during power failure is improved, but device complexity and component count increase

Engineering Contradiction:
Improvedata integrityVSAvoidcomponent count
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the SPD information storage function into the existing non-volatile memory component that is already present on the memory module for backup power purposes. Instead of adding a separate EEPROM or non-volatile memory device, the system utilizes the flash memory that is already integrated on the module to store both backup data and SPD parameters, thereby maintaining data integrity while avoiding increased component count

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The non-volatile memory component is designed to serve multiple functions: it acts as both a backup power storage medium for preserving volatile memory data during power failures and as a repository for SPD information. This multi-functionality eliminates the need for dedicated separate components for each function, resolving the contradiction between reliability improvement and device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If a larger backup power source is used to ensure complete data backup, then data integrity is improved, but cost and power consumption increase

Engineering Contradiction:
Improvedata integrityVSAvoidbackup power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system implements selective backup of only the critical SPD information and essential data parameters to non-volatile memory during power failure events, rather than attempting to backup the entire volatile memory contents. This partial action approach ensures data integrity for essential operations while minimizing the energy requirements and size of the backup power source

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The SPD information is pre-stored in the non-volatile memory during normal operation before power failure occurs. When power is lost, the controller immediately retrieves this pre-stored information without requiring extensive backup operations, thereby reducing the duration and energy consumption of the backup power source while ensuring data integrity

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8566639B2Flash backed DRAM module with state of health and/or status information accessible through a configuration data bus
Publication Date: 2013.10.22 WESTERN DIGITAL TECHNOLOGIES INC
  • US8566639B2 patent drawing
  • US8566639B2 patent drawing
  • US8566639B2 patent drawing

AI summary

A memory device includes: volatile memory; an interface for connecting to a backup power source; non-volatile memory; a first configuration data bus for accessing parameters describing substantially permanent characteristics of the volatile memory; a second configuration data bus for accessing at least one of state of health information of the backup power source and status information of the memory device, wherein the first configuration data bus and the second configuration data bus implement a same bus protocol; a controller programmed to detect a loss of power of a primary power source and move data from the volatile memory to the non-volatile memory, wherein configuration information of the controller is at least one of readable and writable through the first configuration data bus; and wherein at least one of the state-of-health information and the status information is at least one of readable and writable through the second configuration data bus.