Flash Memory Bit Line Discharge via High-Voltage nMOS Transistors
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Solution Overview
Problem
Existing flash memory technologies face issues with inefficient bit-line discharge during erase operations, leading to potential junction breakdown and premature aging of cells, especially when multiple word lines or blocks are erased simultaneously, due to weak capacitive coupling and unknown final bit-line voltage values.
Innovation Solution
The introduction of a discharge path using high-voltage nMOS transistors to connect bit lines to a common node, allowing direct current discharge after the erase pulse, ensuring bit lines are pulled down to a desired voltage, and the use of sensing circuits to determine when both bit-line and p-well bulk region voltages are below a certain level for safe discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are left floating during erase pulse to avoid cell damage, then cell reliability is improved, but bit-line discharge efficiency deteriorates leading to unknown final voltage values and potential junction breakdown
Solution Approach 1:
The patent applies preliminary action by pre-configuring discharge paths using high-voltage nMOS transistors before the erase operation begins. These transistors are prepared in a specific state (gate voltage set to intermediate level) during the programming phase, so that when the erase pulse is applied and bit lines float, the discharge path is already in place and ready to immediately discharge bit lines after erasure, ensuring they reach a known safe voltage level and preventing junction breakdown.
2Productivity
If multiple word lines or blocks are erased simultaneously, then productivity is improved, but bit-line discharge reliability deteriorates due to weak capacitive coupling
Solution Approach 1:
The patent introduces high-voltage nMOS transistors as intermediary components that provide a direct discharge path for bit lines. These transistors act as mediators between the bit lines and ground, allowing reliable discharge even when multiple word lines or blocks are erased simultaneously. The intermediary transistors compensate for the weak capacitive coupling that occurs during multi-block erasure, ensuring each bit line can be independently and reliably discharged regardless of the number of simultaneous erase operations.
3Manufacturing precision
If discharge path is added using high-voltage nMOS transistors, then bit-line discharge efficiency is improved, but device complexity increases
Solution Approach 1:
The patent achieves universality by designing the high-voltage nMOS transistors to serve multiple functions: they act as discharge path switches during erase operations, serve as protection elements against voltage spikes, and can be integrated into existing flash memory block structures. The same transistor design and control mechanism can be replicated across multiple blocks and word lines, providing a scalable solution that improves bit-line discharge efficiency without proportionally increasing overall system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures efficient bit-line discharge even after p-well discharge ends, protecting against junction breakdown and improving reliability, endurance, and retention capabilities of flash memory by maintaining bit lines at a low voltage close to ground, even during simultaneous erasure of multiple word lines or strings.
Implementation Method 1
The introduction of a discharge path using high-voltage nMOS transistors to connect bit lines to a common node, allowing direct current discharge after the erase pulse
Implementation Method 2
the use of sensing circuits to determine when both bit-line and p-well bulk region voltages are below a certain level for safe discharge
Implementation Method 3
This rising of the bit lines can be caused by two effects. First, the p-well bulk region, the non-erasing word lines, and the common source-line strap can be capacitively coupled to bit lines.
Data Source
AI summary
Disclosed here in a method that comprises performing an erase operation on multiple cells in a memory device, the performing comprising applying an erase voltage to the multiple cells, bit lines coupled to the multiple cells being thereby charged up; and discharging the bit lines by coupling the bit lines to a discharging line through a DC path.